TLV320AIC3268_15 Datasheet, PDF (70/263 Pages) Texas Instruments – TLV320AIC3268 Low Power Stereo Audio Codec With 105dB DAC, DirectPath Headphone and Class-D Speaker Amplifier and Integrated miniDSP

TLV320AIC3268
SLAS953A – JANUARY 2014 – REVISED FEBRUARY 2014
www.ti.com
Divider
ASI2_BDIV
ASI3_BDIV
ASI1_WDIV
ASI2_WDIV
ASI3_WDIV
Table 27. ASI1, ASI2, and ASI3 Bit and Word Clock Dividers (continued)
Bits
B0_P4_R28_D[6:0]
B0_P4_R44_D[6:0]
B0_P4_R13_D[6:0]
B0_P4_R29_D[6:0]
B0_P4_R45_D[6:0]
Range
1, 2, … 127, 128
1, 2, … 127, 128
32, 33, … 127, 128
32, 33, … 127, 128
32, 33, … 127, 128
Selector
ASI1_BCLK_OUT
ASI2_BCLK_OUT
ASI3_BCLK_OUT
ASI1_BDIV_CLKIN
ASI2_BDIV_CLKIN
ASI3_BDIV_CLKIN
ASI1_WCLK_OUT
ASI2_WCLK_OUT
ASI3_WCLK_OUT
Table 28. ASI1, ASI2, and ASI3 Bit and Word Clock Selection
Bits
B0_P4_R14_D[6:4]
B0_P4_R30_D[6:4]
B0_P4_R46_D[6:4]
B0_P4_R11_D[1:0]
B0_P4_R27_D[1:0]
B0_P4_R43_D[1:0]
B0_P4_R14_D[2:0]
B0_P4_R30_D[2:0]
B0_P4_R46_D[2:0]
Inputs
ASI1_BDIV_OUT, ASI2_BDIV_OUT, ASI3_BDIV_OUT, ASI2_BCLK,
ASI3_BCLK
ASI1_BDIV_OUT, ASI2_BDIV_OUT, ASI3_BDIV_OUT, ASI1_BCLK,
ASI3_BCLK
ASI1_BDIV_OUT, ASI2_BDIV_OUT, ASI3_BDIV_OUT, ASI1_BCLK,
ASI2_BCLK
DAC_CLK, DAC_MOD_CLK, ADC_CLK, ADC_MOD_CLK
DAC_CLK, DAC_MOD_CLK, ADC_CLK, ADC_MOD_CLK
DAC_CLK, DAC_MOD_CLK, ADC_CLK, ADC_MOD_CLK
DAC_FS, ADC_FS, ASI1_WDIV_OUT, ASI2_WDIV_OUT, ASI3_WDIV_OUT,
ASI2_WCLK, ASI3_WCLK
DAC_FS, ADC_FS, ASI1_WDIV_OUT, ASI2_WDIV_OUT, ASI3_WDIV_OUT,
ASI1_WCLK, ASI3_WCLK
DAC_FS, ADC_FS, ASI1_WDIV_OUT, ASI2_WDIV_OUT, ASI3_WDIV_OUT,
ASI1_WCLK, ASI2_WCLK
Additionally a general purpose clock CLKOUT can be driven out on DOUT1, WCLK2, BCLK2, GPIO1, GPIO2, or
GPO1 according to the settings in Table 29.
Clock Output
DOUT1
WCLK2
BCLK2
GPIO1
GPIO2
MISO_GPO1
Table 29. CLKOUT Selection
Bits
B0_P4_R67_D[4:1] = ’0011’
B0_P4_R69_D[5:2] = ’0100’
B0_P4_R70_D[5:2] = ’0100’
B0_P4_R86_D[6:2] = ’00100’
B0_P4_R87_D[6:2] = ’00100’
B0_P4_R96_D[4:1] = ”0011’
70
Submit Documentation Feedback
Product Folder Links: TLV320AIC3268
Copyright © 2014, Texas Instruments Incorporated