TLV320AIC3268_15 Datasheet, PDF (206/263 Pages) Texas Instruments – TLV320AIC3268 Low Power Stereo Audio Codec With 105dB DAC, DirectPath Headphone and Class-D Speaker Amplifier and Integrated miniDSP

TLV320AIC3268
SLAS953A – JANUARY 2014 – REVISED FEBRUARY 2014
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BIT
D7-D0
Book 0 / Page 4 / Register 38: Reserved Register - 0x00 / 0x04 / 0x26 (B0_P4_R38)
READ/
WRITE
RESET
VALUE
DESCRIPTION
R
0000 0000 Reserved. Write only default values.
BIT
D7-D3
D2-D0
Book 0 / Page 4 / Register 39: ASI3, ADC Input Control - 0x00 / 0x04 / 0x27 (B0_P4_R39)
READ/
WRITE
RESET
VALUE
DESCRIPTION
R
0000 0 Reserved. Write only default values.
R/W
000
ASI3 ADC Input Control
000: ASI3 digital audio output data source disabled (No serial data output on external ASI3 bus.
ASI3 digital output is tri-stated.)
001: ASI3_DataOutput[1:2] data is sourced from miniDSP_ADataOutput[1:2]
010: ASI3_DataOutput[1:2] is sourced from ASI1_DataInput[1:2] (ASI1-to-ASI3 loopback)
011: ASI3_DataOutput[1:2] is sourced from ASI2_DataInput[1:2] (ASI2-to-ASI3 loopback)
100: ASI3_DataOutput[1:2] is sourced from ASI3_DataInput[1:2] (ASI3-to-ASI3 loopback)
101: Reserved. Do not use.
110: ASI3_DataOutput[1:2] is sourced from miniDSP_A_DataOutput[5:6]
111: Reserved. Do not use.
Book 0 / Page 4 / Register 40: ASI3, DAC Output Control - 0x00 / 0x04 / 0x28 (B0_P4_R40)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D6
R/W
00
ASI3 Left DAC Datapath
00: ASI3 Left DAC Datapath = Off
01: ASI3 Left DAC Datapath = Left Data
10: ASI3 Left DAC Datapath = Right Data
11: ASI3 Left DAC Datapath = Mono Mix of Left and Right
D5-D4
R/W
00
ASI3 Right DAC Datapath
00: ASI3 Right DAC Datapath = Off
01: ASI3 Right DAC Datapath = Right Data
10: ASI3 Right DAC Datapath = Left Data
11: ASI3 Right DAC Datapath = Mono Mix of Left and Right
D3-D0
R
0000 Reserved. Write only default values.
BIT
D7-D0
Book 0 / Page 4 / Register 41: Reserved Register - 0x00 / 0x04 / 0x29 (B0_P4_R41)
READ/
WRITE
RESET
VALUE
DESCRIPTION
R
0000 0000 Reserved. Write only default values.
Book 0 / Page 4 / Register 42: ASI3, Word Clock and Bit Clock Control Register - 0x00 / 0x04 / 0x2A
(B0_P4_R42)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D2
R
000000 Reserved. Write only default values.
D1
R/W
0
ASI3 Audio Bit Clock Polarity Control
0: Default Bit Clock polarity
1: Bit Clock is inverted w.r.t. default polarity
D0
R/W
0
ASI3 Bit Clock and Word Clock Power control
0: ASI3 Bit Clock and ASI3 Word Clock buffers are powered down when the codec is powered
down or ASI3 is inactive
1: ASI3 Bit Clock and Word Clock buffers are powered up when they are used in clock generation
even when the codec is powered down
Book 0 / Page 4 / Register 43: ASI3, Bit Clock N Divider Input Control - 0x00 / 0x04 / 0x2B (B0_P4_R43)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
Reserved. Write only default values.
D6
R/W
0
Reserved. Write only default values.
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