TS12A4514_15 Datasheet, PDF (7/18 Pages) Texas Instruments – SPST CMOS ANALOG SWITCHES

TS12A4514, TS12A4515
www.ti.com ................................................................................................................................................... SCDS193D – AUGUST 2006 – REVISED MARCH 2009
APPLICATION INFORMATION
Power-Supply Considerations
The TS12A4514/TS12A4515 construction is typical of most CMOS analog switches, except that they have only
two supply pins: V₊ and GND. V₊ and GND drive the internal CMOS switches and set their analog voltage limits.
Reverse ESD-protection diodes are internally connected between each analog-signal pin and both V₊ and GND.
One of these diodes conducts if any analog signal exceeds V₊ or GND.
Virtually all the analog leakage current comes from the ESD diodes to V₊ or GND. Although the ESD diodes on a
given signal pin are identical and, therefore, fairly well balanced, they are reverse biased differently. Each is
biased by either V₊ or GND and the analog signal. This means their leakages will vary as the signal varies. The
difference in the two diode leakages to the V₊ and GND pins constitutes the analog-signal-path leakage current.
All analog leakage current flows between each pin and one of the supply terminals, not to the other switch
terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity.
There is no connection between the analog-signal paths and V₊ or GND.
V₊ and GND also power the internal logic and logic-level translators. The logic-level translators convert the logic
levels to switched V₊ and GND signals to drive the analog signal gates.
Logic-Level Thresholds
The logic-level thresholds are CMOS/TTL compatible when V₊ is 5 V. As V₊ is raised, the level threshold
increases slightly. When V₊ reaches 12 V, the level threshold is about 3 V – above the TTL-specified high-level
minimum of 2.8 V, but still compatible with CMOS outputs.
CAUTION:
If the user is using the TS12A4514 or TS12A4515 with a V+ supply of 3 V, then
the control input (IN) voltage should not exceed V+, otherwise the output levels
can exceed 3 V and violate the absolute maximum rating, potentially damaging
the device.
High-Frequency Performance
In 50-Ω systems, signal response is reasonably flat up to 250 MHz (see Typical Operating Characteristics).
Above 20 MHz, the on response has several minor peaks that are highly layout dependent. The problem is not in
turning the switch on; it is turning it off. The OFF-state switch acts like a capacitor and passes higher frequencies
with less attenuation. At 10 MHz, OFF isolation is about –45 dB in 50-Ω systems, decreasing (approximately 20
dB per decade) as frequency increases. Higher circuit impedances also make OFF isolation decrease. OFF
isolation is about 3 dB above that of a bare IC socket, and is due entirely to capacitive coupling.
Test Circuits/Timing Diagrams
V₊
V₊
NO
TS12A4514
TS12A4515
V_IN
IN
COM
50 Ω
GND
V_NO or V_NC = 0 V
V_OUT
C_L
1000 pF
V₊
V_IN
0V
V_OUT
TS12A4514 TS12A4515
∆V_OUT
∆V_OUT is the measured voltage due to charge
transfer error Q when the channel turns off.
Q = DV_OUT x C_L
Figure 1. Charge Injection
Copyright © 2006–2009, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): TS12A4514 TS12A4515