THS4541_15 Datasheet, PDF (7/61 Pages) Texas Instruments – THS4541 Negative Rail Input, Rail-to-Rail Output, Precision, 850-MHz Fully Differential Amplifier

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THS4541
SLOS375A – AUGUST 2014 – REVISED SEPTEMBER 2014
Electrical Characteristics: Vs+ – Vs– = 5 V (continued)
At T_A ≈ 25°C, Vocm = open (defaults midsupply), V_OUT = 2 V_PP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V,
single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 61 for an ac-coupled gain of a
2-V/V test circuit, and Figure 63 for a dc-coupled gain of a 2-V/V test circuit.
PARAMETER
TEST CONDITIONS
TEST
MIN
TYP
MAX UNIT
LEVEL ⁽¹⁾
POWER SUPPLY
Specified operating voltage
2.7
5.0
5.4
V
B
±PSRR
Quiescent operating current
Power-supply rejection ratio
T_A = +25°C, Vs+ = 5.0 V
T_A = –40°C to 125°C
Either supply pin to differential Vout
9.7
10.1
10.5 mA
A
9.4
10.1
11 mA
B
85
100
dB
A
POWER DOWN
Enable voltage threshold
Vs– + 1.7
V
A
Disable voltage threshold
Vs– + 0.7
V
A
Disable pin bias current
PD = Vs– → Vs+
20
50
nA
B
Power-down quiescent current
PD = Vs– + 0.7 V
PD = Vs–
6
30
µA
A
2
8
µA
A
Turn-on time delay
Time from PD = low to Vout = 90% of final
value
100
ns
C
Turn-off time delay
Time from PD = low to Vout = 10% of final
value
OUTPUT COMMON-MODE VOLTAGE CONTROL⁽⁴⁾
60
ns
C
Small-signal bandwidth
Slew rate⁽⁵⁾
Vocm = 100 mV_PP
Vocm = 2-V step
150
MHz
C
400
V/µs
C
Gain
0.975
0.982
0.995 V/V
A
Input bias current
Considered positive out of node
–0.7
0.1
0.7
µA
A
Input impedance
Vocm input driven to (Vs+ – Vs–) / 2
47 || 1.2
kΩ || pF
C
Default voltage offset from
(Vs+ – Vs–) / 2
Vocm pin open
–40
±8
40 mV
A
T_A = 25°C
–5
CM Vos Common-mode offset voltage
Vocm input driven to ^TA ^{= 0°C to 70°C}
(Vs+ – Vs–) / 2
T_A = –40°C to 85°C
–6
–6.2
T_A = –40°C to 125°C
–7.0
Common-mode offset voltage
drift ⁽⁶⁾
Vocm input driven to (Vs+ – Vs–) / 2
–20
±2
5 mV
A
±2
5.8 mV
B
±2
6.2 mV
B
±2
7.08 mV
B
±4
+20 µV/°C
B
T_A = 25°C
0.88
Common-mode loop supply
< ±12-mV shift from ^TA ^{= 0°C to 70°C}
0.91
headroom to negative supply
midsupply CM Vos _{TA = –40°C to 85°C}
0.94
T_A = –40°C to 125°C
0.94
T_A = 25°C
1.1
Common-mode loop supply
< ±12-mV shift from ^TA ^{= 0°C to 70°C}
1.15
headroom to positive supply
midsupply CM Vos _{TA = –40°C to 85°C}
1.2
T_A = –40°C to 125°C
1.2
V
A
V
B
V
B
V
B
V
A
V
B
V
B
V
B
(4) Specifications are from the input Vocm pin to the differential output average voltage.
(5) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (V_P / √2) · 2π · f_–3dB.
(6) Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at
the at the maximum-range ambient-temperature end points, computing the difference, and dividing by the temperature range. Maximum
drift set by distribution of a large sampling of devices. Drift is not specified by test or QA sample test.
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