THS4541_15 Datasheet, PDF (35/61 Pages) Texas Instruments – THS4541 Negative Rail Input, Rail-to-Rail Output, Precision, 850-MHz Fully Differential Amplifier

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THS4541
SLOS375A – AUGUST 2014 – REVISED SEPTEMBER 2014
9.3 Feature Description
9.3.1 Differential I/O
The THS4541 combines a core differential I/O, high-gain block with an output common-mode sense that is
compared to a reference voltage and then fed back into the main amplifier block to control the average output to
that reference. The differential I/O block is a classic, high open-loop gain stage with a dominant pole at
approximately 900 Hz. This voltage feedback structure projects a single-pole, unity-gain Aol at 850 MHz (gain
bandwidth product). The high-speed differential outputs include an internal averaging resistor network to sense
the output common-mode voltage. This voltage is compared by a separate Vcm error amplifier to the voltage on
the Vocm pin. If floated, this reference is at half the total supply voltage across the device using two 100-kΩ
resistors. This Vcm error amplifier transmits a correction signal into the main amplifier to force the output average
voltage to meet the target voltage on the Vocm pin. The bandwidth of this error amplifier is approximately the
same bandwidth as the main differential I/O amplifier.
The differential outputs are collector outputs to obtain the rail-to-rail output swing. These outputs are relatively
high-impedance, open-loop sources; however, closing the loop provides a very low output impedance for load
driving. No output current limit or thermal shutdown features are provided in this lower-power device. The
differential inputs are PNP inputs to provide a negative-rail input range.
To operate the THS4541 for the RGT package, connect external resistors from the FB– pin to the IN+ pins, and
the FB+ pin to the IN– pins. For the RUN package, connect the OUT– pin to the IN+ pin through an Rf, and the
OUT+ pin to the IN– pin through the same value of Rf. Bring in the inputs through additional resistors to the IN+
and IN– pins. The differential I/O op amp operates similarly to an inverting op amp structure where the source
must drive the input resistor and the gain is the ratio of the feedback to the input resistor.
9.3.2 Power-Down Control Pin (PD)
The THS4541 includes a power-down control pin, PD. This pin must be asserted high for correct amplifier
operation. The PD pin cannot be floated because there is no internal pullup or pulldown resistor on this pin to
reduce disabled power consumption. Asserting this pin low (within 0.7 V of the negative supply) puts the
THS4541 into a very low quiescent state (approximately 2 µA). Switches in the default Vocm resistor string open
to eliminate the fixed bias current (25 µA) across the supply in this 200-kΩ voltage divider to midsupply.
9.3.2.1 Operating the Power Shutdown Feature
Assert this CMOS input pin to the desired voltage for operation. For applications that require the device to only
be powered on when the supplies are present, tie the PD pin to the positive supply voltage.
When the PD pin is somewhat below the positive supply pin, slightly more quiescent current is drawn; see
Figure 56. For the minimum-on power, assert this pin to the positive supply.
The disable operation is referenced from the negative supply; normally, ground. For split-supply operation, with
the negative supply below ground, a disable control voltage below ground is required to turn the THS4541 off
when the negative supply exceeds –0.7 V.
For single-supply operation, a minimum of 1.7 V above the negative supply (ground, in this case) is required to
assure operation. This minimum logic-high level allows for direct operation from 1.8-V supply logic.
9.3.3 Input Overdrive Operation
The THS4541 input stage architecture is intrinsically robust to input overdrives with the series input resistor
required by all applications. High input overdrives cause the outputs to limit into their maximum swings with the
remaining input current through the Rg resistors absorbed by internal, back-to-back protection diodes across the
two inputs. These diodes are normally off in application, and only turn on to absorb the currents that a large input
overdrive might produce through the source impedance and or the series Rg elements required by all designs.
Figure 12 and Figure 30 illustrate the exceptional output limiting and short recovery time for an input overdrive
that is attempting to drive the outputs to two times the available swing.
The internal input diodes can safely absorb up to ±15 mA in an overdrive condition. For designs that require
more current to be absorbed, consider adding an external protection diode such as the BAV99 device used in the
example ADC interface design of Figure 80.
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