THS1401-EP Datasheet, PDF (7/27 Pages) Texas Instruments – 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA

THS1401-EP THS1403-EP THS1408-EP
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SGLS129A – JULY 2002 – REVISED NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
sample timing
The THS1401/3/8 core is based on a pipeline architecture with a latency of 9.5 samples. The conversion results
appear on the digital output 9.5 clock cycles after the input signal was sampled.
S11
S12
S9
Analog
S10
Input
tw(CLK)
tw(CLK)
CLK
td
Data
Out
C1
C2
C3
Figure 1. Sample Timing
The parallel interface of the THS1401/3/8 ADC features 3-state buffers, making it possible to directly connect it to
a data bus. The output buffers are enabled by driving the OE input low.
Besides the sample results, it is also possible to read back the values of the control register, the PGA register, and
the offset register. Which register is read is determined by the address inputs A[1,0]. The ADC results are available
at address 0.
The timing of the control signals is described in the following sections.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
7