SN74CB3T3383 Datasheet, PDF (7/19 Pages) Texas Instruments – 10-BIT FET BUS-EXCHANGE SWITCH 2.5V/3.3-V LOW-VOLTAGE BUSSWITCH WITH 5-V-TOLERANT LEVEL SHIFTER

SN74CB3T3383
10ĆBIT FET BUSĆEXCHANGE SWITCH
2.5ĆV/3.3ĆV LOWĆVOLTAGE BUS SWITCH WITH 5ĆVĆTOLERANT LEVEL SHIFTER
SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
Input Generator
VG1
50 Ω
Input Generator
VG2
50 Ω
VIN
50 Ω
VI
50 Ω
VCC
DUT
TEST CIRCUIT
VO
CL
(see Note A)
2 × VCC
RL
S1
Open
GND
RL
TEST
tpd(s)
tPLZ/tPZL
VCC
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
tPHZ/tPZH
2.5 V ± 0.2 V
3.3 V ± 0.3 V
S1
Open
Open
2 × VCC
2 × VCC
Open
Open
RL
500 Ω
500 Ω
500 Ω
500 Ω
500 Ω
500 Ω
VI
3.6 V or GND
5.5 V or GND
GND
GND
3.6 V
5.5 V
CL
30 pF
50 pF
30 pF
50 pF
30 pF
50 pF
V_∆
0.15 V
0.3 V
0.15 V
0.3 V
Output
Control
(VIN)
VCC/2
VCC/2
VCC
0V
Output
Control
(VIN)
VCC/2
VCC/2
VCC
0V
tPLH
tPHL
Output
VCC/2
VOH
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPZL
tPZH
Output
Waveform 2
S1 at Open
(see Note B)
VCC/2
VCC/2
tPLZ
VCC
VOL + V_∆
VOL
tPHZ
VOH
VOH − V_∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Test Circuit and Voltage Waveforms
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