SN74AUC2G241_08 Datasheet, PDF (7/14 Pages) Texas Instruments – DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS

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SN74AUC2G241
DUAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES535C – DECEMBER 2003 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
C_L
(see Note A)
R_L
R_L
2 × V_CC
S1
Open
GND
LOAD CIRCUIT
TEST
t /t _{PLH PHL}
t /t _{PLZ PZL}
t /t _{PHZ PZH}
V_CC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
C_L
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
S1
Open
2 × V_CC
GND
R_L
2 kW
2 kW
2 kW
2 kW
2 kW
1 kW
500 W
V_D
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
Input
t_W
V_CC/2
V_CC/2
VOLTAGE WAVEFORMS
PULSE DURATION
Timing Input
V_CC
Data Input
0V
V_CC
V_CC/2
0V
t_su
t_h
V_CC
V_CC/2
V_CC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
V_CC/2
V_CC
V_CC/2
0V
t_PLH
Output
V_CC/2
t_PHL
V_CC/2
V_OH
V_OL
t_PHL
t_PLH
V_OH
Output
V_CC/2
V_CC/2
V_OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at 2 × V_CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V_CC/2
t_PZL
V_CC/2
t_PLZ
V_CC
0V
V_CC/2
V_CC
V_OL + V_D
V_OL
t_PZH
t_PHZ
V_CC/2
V_OH – V_D
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
V_OH
»0 V
NOTES: A. C_L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, Z_O = 50 W,
slew rate ³ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t_PLZ and t_PHZ are the same as t_dis.
F. t_PZL and t_PZH are the same as t_en.
G. t_PLH and t_PHL are the same as t_pd.
Figure 1. Load Circuit and Voltage Waveforms
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