ONET1151PRGTT Datasheet, PDF (7/25 Pages) Texas Instruments – 11.3 Gbps Limiting Amplifier

ONET1151P
www.ti.com
SLLSEH8 – SEPTEMBER 2013
LOSS OF SIGNAL DETECTION
The loss of signal detection is done by 2 separate level detectors to cover a wide dynamic range. The peak
values of the input signal and the output signal of the gain stage are monitored by the peak detectors. The peak
values are compared to a pre-defined loss of signal threshold voltage inside the loss of signal detection block. As
a result of the comparison, the LOS signal, which indicates that the input signal amplitude is below the defined
threshold level, is generated. The LOS assert level is settable through the serial interface. There are 2 LOS
ranges settable with the LOSRNG bit (bit 2 register 0). By setting LOSRNG = 1, the high range of the LOS assert
values are used (35 mV_p-p to 80 mV_p-p) and by setting LOSRNG = 0, the low range of the LOS assert values are
used (15 mV_p-p to 35 mV_p-p).
There are 128 possible internal LOS settings (7bit) for each LOS range to adjust the LOS assert level. If the LOS
register selection bit is set low, LOSSEL = 0 (bit 7 of register 11), then the default LOS assert level of
approximately 25 mV_p-p is used. If the register selection bit is set high, LOSSEL = 1 (bit 7 of register 11), then the
content of LOS[0..6] (register 11) is used to set the LOS assert level.
An LOS output masking time can be enabled on the raising and falling edges of the LOS output signal. The LOS
rising edge masking time is enabled by setting LOSTMRENA = 1 (bit 7 of register 13) and the time programmed
using LOSTMR[0..6] (register 13). The LOS falling edge masking time is enabled by setting LOSTMFENA = 1 (bit
7 of register 12) and the time programmed using LOSTMF[0..6] (register 12).This feature is used to mask a false
input to the limiting amplifier after a loss of signal has occurred or when the input signal is re-applied. The
masking time can be set from 10 μs to 2 ms.
2-WIRE INTERFACE AND CONTROL LOGIC
The ONET1151P uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCK, are
driven, respectively, by the serial data and serial clock from a microcontroller, for example. Both inputs include
100-kΩ pull-up resistors to VCC. For driving these inputs, an open drain output is recommended.
The 2-wire interface allows write access to the internal memory map to modify control registers and read access
to read out control and status signals. The ONET1151P is a slave device only which means that it can not initiate
a transmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. The
master device provides the clock signal as well as the START and STOP commands. The protocol for a data
transmission is as follows:
1. START command
2. 7 bit slave address (1000100) followed by an eighth bit which is the data direction bit (R/W). A zero indicates
a WRITE and a 1 indicates a READ.
3. 8-bit register address
4. 8-bit register data word
5. STOP command
Regarding timing, the ONET1151P is I²C compatible. The typical timing is shown in Figure 3 and complete data
transfer is shown in Figure 4. Parameters for Figure 3 are defined in Table 2.
Bus Idle: Both SDA and SCK lines remain HIGH.
Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCK line is HIGH,
defines a START condition (S). Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCK line is HIGH
defines a STOP condition (P). Each data transfer is terminated with a STOP condition; however, if the master still
wishes to communicate on the bus, it can generate a repeated START condition and address another slave
without first generating a STOP condition.
Data Transfer: Only one data byte can be transferred between a START and a STOP condition. The receiver
acknowledges the transfer of data.
Copyright © 2013, Texas Instruments Incorporated
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