ONET1151PRGTT Datasheet, PDF (2/25 Pages) Texas Instruments – 11.3 Gbps Limiting Amplifier

ONET1151P
SLLSEH8 – SEPTEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
BLOCK DIAGRAM
A simplified block diagram of the ONET1151P is shown in Figure 1.
This compact, low power 11.3 Gbps limiting amplifier consists of a high-speed data path with offset cancellation
block (DC feedback) combined with an analog settable input threshold adjust, a loss of signal detection block
using 2 peak detectors, a two-wire interface with a control-logic block and a bandgap voltage reference and bias
current generation block.
COC1 COC2
VCC
GND
DIN+
DIN-
100
Input
Buffer
Offset
Cancellation
Gain Stage
Gain Stage
LOS Detection
Output
Buffer
VCC
50 50
DOUT+
DOUT-
LOS
SDA
SDA
8 Bit Register Settings
8 Bit Register Input Threshold
SCK
SCK
4 Bit
4 Bit CPRNG and DE
DIS
DIS
3 Bit
8 Bit Register
8 Bit Register
Amplitude
Settings
LOS Adjust
8 Bit Register LOS Masking
8 Bit Register LOS Masking
2-Wire Interface &
Control Logic
Power-On
Reset
Bandgap Voltage
Reference and
Bias Current
Generation
Figure 1. Simplified Block Diagram of the ONET1151P
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