DS90C187 Datasheet, PDF (7/21 Pages) Texas Instruments – Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer

Symbol
TPPOS0
TPPOS1
TPPOS2
TPPOS3
TPPOS4
TPPOS5
TPPOS6
ΔTPPOS
TCCS
TJCC
TPLLS
TPDD
TSD
TLAT
Parameter
Transmitter Output Pulse Positions Normalized Figure 9
for Bit 0
Transmitter Output Pulse Positions Normalized
for Bit 1
Transmitter Output Pulse Positions Normalized
for Bit 2
Transmitter Output Pulse Positions Normalized
for Bit 3
Transmitter Output Pulse Positions Normalized
for Bit 4
Transmitter Output Pulse Positions Normalized
for Bit 5
Transmitter Output Pulse Positions Normalized
for Bit 6
Variation in Transmitter Pulse Position (Bit 6 —
Bit 0)
LVDS Channel to Channel Skew
Jitter Cycle-to-Cycle
MODE0, MODE1 = 0,
f = 105 MHz,
(Note 4)
Phase Lock Loop Set (Enable Time)
Figure 7
Powerdown Delay
Figure 8
(Note 5)
Latency Delay
MODE0 = 0,
MODE1 = 1 or 0
Figure 10
(Note 4)
Latency Delay for Single Pixel In / Dual Pixel
Out Mode
MODE0 = 1,
MODE1 = 0
Figure 10
(Note 4)
Min
Typ
Max
Units
1
UI
2
UI
3
UI
4
UI
5
UI
6
UI
7
UI
±0.06
UI
110
ps
0.028
0.035
UI
1
ms
100
ns
2*TCIP + 2*TCIP +
ns
10.54
13.96
9*TCIP + 9*TCIP +
ns
4.19
6.36
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_DD, V_DDTX and V_DDP = 1.8V and T _A = +25°C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V_OD and ΔV_OD).
Note 4: Parameter is guaranteed by characterization and is not tested at final test.
Note 5: Parameter is guaranteed by design and is not tested at final test.
7
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