DRV8301 Datasheet, PDF (7/26 Pages) Texas Instruments – Three Phase Pre-Driver with Dual Current Shunt Amplifiers and Buck Regulator

DRV8301
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RECOMMENDED OPERATING CONDITIONS
PVDD1
PVDD2
C_AVDD
C_DVDD
C_GVDD
C_CP
C_BST
I_{DIN_EN}
I_{DIN_DIS}
C_DIN
C_{O_OPA}
R_DTC
I_FAULT
I_OCTW
V_REF
f_gate
T_A
DC supply voltage PVDD1 for normal operation Relative to PGND
DC supply voltage PVDD2 for buck converter
External capacitance on AVDD pin (ceramic cap) 20% tolerance
External capacitance on DVDD pin (ceramic cap) 20% tolerance
External capacitance on GVDD pin (ceramic cap) 20% tolerance
Flying cap on charge pump pins (between CP1 and CP2) (ceramic cap) 20% tolerance
Bootstrap cap (ceramic cap)
Input current of digital pins when EN_GATE is high
Input current of digital pins when EN_GATE is low
Maximum capacitance on digital input pin
Maximum output capacitance on outputs of shunt amplifier
Dead time control resistor range. Time range is 50ns (-GND) to 500ns (150kΩ) with a
linear approximation.
FAULT pin sink current. Open-drain
V = 0.4 V
OCTW pin sink current. Open-drain
V = 0.4 V
External voltage reference voltage for current shunt amplifiers
Operating switching frequency of gate driver
Qg(TOT) = 25 nC or total 30 mA gate
drive average current
Ambient temperature
SLOS719 – AUGUST 2011
MIN TYP MAX
8
60
3.5
60
1
1
2.2
22
100
100
1
10
20
UNITS
V
V
µF
µF
µF
nF
nF
µA
µA
pF
pF
0
150 kΩ
2 mA
2 mA
2
6V
200 kHz
–40
125 °C
ELECTRICAL CHARACTERISTICS
PVDD = 8-60 V, T_C = 25°C, unless specified under test condition
PARAMETER
TEST CONDITIONS
INPUT PINS: INH_X, INL_X, M_PWM (SCS), M_OC (SDI), GAIN(SDO), EN_GATE, DC_CAL
V_IH
V_IL
R_{EN_GATE}
R_{INH_X}
High input threshold
Low input threshold
Internal pull down resistor for EN_GATE
Internal pull down resistor for high side PWMs
(INH_A, INH_B, and INH_C)
EN_GATE high
R_{INH_X}
Internal pull down resistor for low side PWMs
(INL_A, INL_B, and INL_C)
EN_GATE high
R_SCS
Internal pull down resistor for SCS
R_SDI
Internal pull down resistor for SDI
R_{DC_CAL}
Internal pull down resistor for DC_CAL
R_SCLK
Internal pull down resistor for SCLK
OUTPUT PINS: FAULT AND OCTW
EN_GATE high
EN_GATE high
EN_GATE high
EN_GATE high
V_OL
Low output threshold
V_OH
High output threshold
I_O = 2 mA
External 47 kΩ pull up resistor connected to
3-5.5 V
I_OH
Leakage Current on Open Drain Pins When
Logic High (FAULT and OCTW)
MIN TYP MAX UNIT
2
V
0.8 V
100
kΩ
100
kΩ
100
kΩ
100
kΩ
100
kΩ
100
kΩ
100
kΩ
0.4 V
2.4
V
1 µA
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): DRV8301
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