DRV8301 Datasheet, PDF (3/26 Pages) Texas Instruments – Three Phase Pre-Driver with Dual Current Shunt Amplifiers and Buck Regulator

DRV8301
www.ti.com
PIN
NAME
NO.
RT_CLK
1
COMP
2
VSENSE
3
PWRGD
4
OCTW
5
FAULT
6
DTC
7
SCS
8
SDI
9
SDO
10
SCLK
11
DC_CAL
12
GVDD
13
CP1
14
CP2
15
EN_GATE
16
INH_A
17
INL_A
18
INH_B
19
INL_B
20
INH_C
21
INL_C
22
DVDD
23
REF
24
SO1
25
SO2
26
AVDD
27
AGND
28
PVDD1
29
SP2
30
SN2
31
SP1
32
SN1
33
SL_C
34
GL_C
35
SH_C
36
GH_C
37
SLOS719 – AUGUST 2011
PIN FUNCTIONS
I/O ⁽¹⁾
DESCRIPTION
I
Resistor timing and external clock for buck regulator. Resistor should connect to GND (power pad) with
very short trace to reduce the potential clock jitter due to noise.
O Buck error amplifier output and input to the output switch current comparator.
I
Buck output voltage sense pin. Inverting node of error amplifier.
I
An open drain output with external pull-up resistor required. Asserts low if buck output voltage is low
due to thermal shutdown, dropout, over-voltage, or EN_BUCK shut down
O Over current or/and over temperature warning indicator. This output is open drain with external pull-up
resistor required. Programmable output mode via SPI registers.
O Fault report indicator. This output is open drain with external pull-up resistor required.
I
Dead-time adjustment with external resistor to GND
I
SPI chip select
I
SPI input
O SPI output
I
SPI clock signal
I
When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset
calibration can be done through external microcontroller.
P Internal gate driver voltage regulator. GVDD cap should connect to GND
P Charge pump pin 1, ceramic cap should be used between CP1 and CP2
P Charge pump pin 2, ceramic cap should be used between CP1 and CP2
I
Enable gate driver and current shunt amplifiers. Control buck via EN_BUCK pin.
I
PWM Input signal (high side), half-bridge A
I
PWM Input signal (low side), half-bridge A
I
PWM Input signal (high side), half-bridge B
I
PWM Input signal (low side), half-bridge B
I
PWM Input signal (high side), half-bridge C
I
PWM Input signal (low side), half-bridge C
P Internal 3.3V supply voltage. DVDD cap should connect to AGND. This is an output, but not specified
to drive external circuitry.
I
Reference voltage to set output of shunt amplfiiers with a bias voltage which equals to half of the
voltage set on this pin. Connect to ADC reference in microcontroller.
O Output of current amplifier 1
O Output of current amplifier 2
P Internal 6V supply voltage, AVDD cap should connect to AGND. This is an output, but not specified to
drive external circuitry.
P Analog ground pin
P Power supply pin for gate driver, current shunt amplifier, and SPI communication. PVDD1 is
independent of buck power supply, PVDD2. PVDD1 cap should connect to GND
I
Input of current amplifier 2 (connecting to positive input of amplifier). Recommend to connect to ground
side of the sense resistor for the best commom mode rejection.
I
Input of current amplifier 2 (connecting to negative input of amplifier).
I
Input of current amplifier 1 (connecting to positive input of amplifier). Recommend to connect to ground
side of the sense resistor for the best commom mode rejection.
I
Input of current amplifier 1 (connecting to negative input of amplifier).
I
Low-Side MOSFET source connection, half-bridge C. Low-side V_DS measured between this pin and
SH_C.
O Gate drive output for Low-Side MOSFET, half-bridge C
I
High-Side MOSFET source connection, half-bridge C. High-side V_DS measured between this pin and
PVDD1.
O Gate drive output for High-Side MOSFET, half-bridge C
(1) KEY: I =Input, O = Output, P = Power
Copyright © 2011, Texas Instruments Incorporated
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