DAC5681Z_15 Datasheet, PDF (7/58 Pages) Texas Instruments – 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC)

DAC5681Z
www.ti.com
SLLS865F – AUGUST 2007 – REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS — DC SPECIFICATION (continued)
over operating free-air temperature range , AVDD = 3.3 V, CLKVDD = 1.8 V, IOVDD = 3.3 V, DVDD = 1.8 V, Iout_FS = 20 mA
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
I_(AVDD)
I_(DVDD)
I_(CLKVDD)
Sleep mode, AVDD supply current
Sleep mode, DVDD supply current
Sleep mode, CLKVDD supply
current
Mode 6 (below)
1
mA
4
mA
2
mA
I_(IOVDD)
Sleep mode, IOVDD supply
current
2
mA
AVDD + IOVDD current, 3.3V
DVDD + CLKVDD current, 1.8V
Power Dissipation
Mode 1: 1X2, PLL = OFF, CLKIN = 983.04 MHz
FDAC = 983.04MHz, IF = 184.32 MHz
4 carrier WCDMA
71
mA
267
mA
715
mW
AVDD + IOVDD current, 3.3V
DVDD + CLKVDD current, 1.8V
Power Dissipation
Mode 2: 1X2, PLL = ON (8X), CLKIN = 122.88 MHz
FDAC = 983.04MHz, IF = 184.32 MHz
4 carrier WCDMA
81
mA
292
mA
790
mW
AVDD + IOVDD current, 3.3V
Mode 3: 1X4, HP/HP, PLL = OFF,
DVDD + CLKVDD current, 1.8V
CLKIN = 983.04 MHz, FDAC = 983.04MHz,
IF = 215.04 MHz
Power Dissipation
4 carrier WCDMA
P
AVDD + IOVDD current, 3.3V
Mode 4: 1X4, HP/HP, PLL = ON (8X),
DVDD + CLKVDD current, 1.8V
CLKIN = 122.88 MHz
FDAC = 983.04MHz, IF = 215.04 MHz
Power Dissipation
DACA on, 4 carrier WCDMA
71
mA
278
mA
735
mW
81
mA
312
mA
830 910 mW
AVDD + IOVDD current, 3.3V
DVDD + CLKVDD current, 1.8V
Power Dissipation
Mode 5: PLL = OFF,
CLKIN = 983.04 MHz, FDAC = 983.04MHz,
Digital Logic Disabled, DAC on SLEEP,
Static Data Pattern
3
mA
117
mA
220
mW
AVDD + IOVDD current, 3.3V
DVDD + CLKVDD current, 1.8V
Power Dissipation
Mode 6: PLL = OFF, CLKIN = OFF
FDAC = OFF, Digital Logic Disabled
DAC on SLEEP, Static Data Pattern
3
mA
6
mA
20
30 mW
PSRR Power supply rejection ratio
DC tested
–0.2
0.2 %FSR/V
T
Operating range
–40
85
°C
ANALOG OUTPUT
f_CLK
t_s(DAC)
t_pd
Maximum output update rate
Output settling time to 0.1%
Output propagation delay
1000
Transition: Code 0x0000 to 0xFFFF
10.4
DAC output is updated on falling edge of DAC clock.
Does not include Digital Latency (see below).
2.5
MSPS
ns
ns
t_r(IOUT)
t_f(IOUT)
Output rise time 10% to 90%
Output fall time 90% to 10%
Digital Latency
No interpolation, PLL Off
x2 interpolation, PLL Off
x4 interpolation, PLL Off
220
ps
220
ps
76
DAC
158
clock
289
cycles
DAC Wake-up Time
Power-up
Time
DAC Sleep Time
IOUT current settling to 1% of IOUT_FS. Measured
from SDENB; Register 0x06, toggle Bit 4 from 1 to 0.
IOUT current settling to less than 1% of IOUT_FS.
Measured from SDENB; Register 0x06, toggle Bit 4
from 0 to 1.
80
μs
80
μs
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