CDC318A Datasheet, PDF (7/12 Pages) Texas Instruments – 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE

CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I²C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
switching characteristics over recommended operating conditions
PARAMETER
FROM
TO
TEST CONDITIONS
MIN MAX
tPLH Low-to-high level propagation delay time
A
SCLOCK↓
Y
SDATA
valid
VCC = 3.3 V ±0.165 V,
See Figure 3
1.2 4.5
2
tPLH Low-to-high level propagation delay time
SDATA↑
Y
VCC = 3.3 V ±0.165 V,
See Figure 3
150
tPHL High-to-low level propagation delay time
A
SCLOCK↓
Y
SDATA
valid
VCC = 3.3 V ±0.165 V,
See Figure 3
1.2 4.5
2
tPHL High-to-low level propagation delay time
SDATA↑
Y
VCC = 3.3 V ±0.165 V,
See Figure 3
150
tPZH
tPZL
Enable time to the high level
Enable time to the low level
OE
Y
1
7
1
7
tPHZ
tPLZ
Disable time from the high level
Disable time from the low level
OE
Y
1
7
1
7
tsk(o) Skew time
A
Y
250
tsk(p) Skew time
A
Y
500
tsk(pr) Skew time
A
Y
1
tr
Rise time
Y
0.5 2.2
tr
Rise time (see Note 5 and
Figure 3)
SDATA
tf
Fall time
CL = 10 pF
CL = 400 pF
Y
6
950
0.5 2.3
tf
Fall time (see Note 5 and
Figure 3)
SDATA
CL = 10 pF
CL = 400 pF
20
250
NOTE 5: This parameter has a lower limit than BUS specification. This allows use of series resistors for current spike protection.
UNIT
ns
µs
ns
ns
µs
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
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