CDC318A Datasheet, PDF (3/12 Pages) Texas Instruments – 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE

CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I²C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
Terminal Functions
TERMINAL
I/O
NAME
NO.
DESCRIPTION
1Y0–1Y3
4, 5, 8, 9
O 3.3-V SDRAM byte 0 clock outputs
2Y0–2Y3
13, 14, 17, 18
O 3.3-V SDRAM byte 1 clock outputs
3Y0–3Y3
31, 32, 35, 36
O 3.3-V SDRAM byte 2 clock outputs
4Y0–4Y3
40, 41, 44, 45
O 3.3-V SDRAM byte 3 clock outputs
5Y0–5Y1
21, 28
O 3.3-V clock outputs provided for feedback control of external phase-locked loops (PLLs)
A
11
OE
38
SCLOCK
25
SDATA
24
I
Clock input
I
Output enable. When asserted, OE puts all outputs in a high-impedance state. A nominal
140-kΩ pullup resistor is internally integrated.
I
I2C serial clock input. A nominal 140-kΩ pullup resistor is internally integrated.
I/O
Bidirectional I2C serial data input/output. A nominal 140-kΩ pullup resistor is internally
integrated.
GND
6, 10, 15, 19, 22, 26,
27, 30, 34, 39, 43
Ground
NC
1, 2, 47, 48
No internal connection. Reserved for future use.
VCC
3, 7, 12, 16, 20, 23,
29, 33, 37, 42, 46
3.3-V power supply
I2C DEVICE ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0 (R/W)
H
H
L
H
L
L
H
—
I2C BYTE 0-BIT DEFINITION†
BIT
DEFINITION
DEFAULT VALUE
7
2Y3 enable (pin 18)
H
6
2Y2 enable (pin 17)
H
5
2Y1 enable (pin 14)
H
4
2Y0 enable (pin 13)
H
3
1Y3 enable (pin 9)
H
2
1Y2 enable (pin 8)
H
1
1Y1 enable (pin 5)
H
0
1Y0 enable (pin 4)
H
† _{When the value of the bit is high, the output is enabled.}
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
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