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CD54HC4020 Datasheet, PDF (7/13 Pages) Texas Instruments – High-Speed CMOS Logic 14-Stage Binary Counter
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CD54HC4020, CD74HC4020, CD54HCT4020, CD74HCT4020
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
TEST
VCC
SYMBOL CONDITIONS (V)
25oC
-40oC TO 85oC -55oC TO 125oC
MIN TYP MAX MIN MAX MIN MAX UNITS
HCT TYPES
Propagation Delay Time
(Figure 2)
CP to Q1’ Output
Qn to Qn + 1
MR to Qn
Output Transition
Input Capacitance
Power Dissipation Capaci-
tance
(Notes 3, 4)
tPLH,
tPHL
CL = 50pF
CL =15pF
tPLH,
tPHL
CL = 50pF
CL =15pF
tPLH,
tPHL
CL = 50pF
CL =15pF
tTLH, tTHL CL = 50pF
CIN CL =15pF
CPD CL =15pF
4.5
-
-
40
-
50
-
5
-
17
-
-
-
-
4.5
-
-
15
-
19
-
5
-
6
-
-
-
-
4.5
-
-
40
-
50
-
5
-
17
-
-
-
-
4.5
-
-
15
-
19
-
-
-
-
10
-
10
-
5
-
30
-
-
-
-
60
ns
-
ns
22
ns
-
ns
60
ns
-
ns
22
ns
10
pF
-
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per package.
4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
trCL
CLOCK
90%
10%
tfCL
50%
10%
tWL
tWL
+
tWH
=
I
fCL
50%
50%
tWH
VCC
GND
trCL = 6ns
CLOCK
2.7V
0.3V
tfCL = 6ns
tWL
+
tWH
=
I
fCL
3V
1.3V
0.3V
1.3V
1.3V
GND
tWL
tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
7
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