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CD54HC4020 Datasheet, PDF (6/13 Pages) Texas Instruments – High-Speed CMOS Logic 14-Stage Binary Counter
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CD54HC4020, CD74HC4020, CD54HCT4020, CD74HCT4020
Prerequisite for Switching Specifications (Continued)
25oC
-40oC TO 85oC
-55oC TO 125oC
PARAMETER
Reset Removal Time
SYMBOL VCC (V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
tREM
2
50
-
65
-
75
-
ns
4.5
10
-
13
-
15
-
ns
6
9
-
11
-
13
-
ns
Reset Pulse Width
tW
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
HCT TYPES
Maximum Input Pulse
Frequency
fMAX
4.5
25
-
20
-
16
-
MHz
Input Pulse Width
Reset Recovery Time
Reset Pulse Width
tW
4.5
20
-
25
-
30
-
ns
tREC
4.5
10
-
13
-
15
-
ns
tW
4.5
20
-
25
-
30
-
ns
Switching Specifications Input tr, tf = 6ns
PARAMETER
TEST
SYMBOL CONDITIONS
VCC
(V)
25oC
-40oC TO 85oC -55oC TO 125oC
MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay Time
(Figure 1)
CP to Q1’ Output
tPLH,
tPHL
CL = 50pF
2
-
- 140
-
175
-
210
ns
4.5
-
-
28
-
35
-
42
ns
Qn to Qn + 1
tPLH,
tPHL
CL =15pF
CL = 50pF
CL = 50pF
5
-
11
-
-
-
-
-
ns
6
-
-
24
-
30
-
36
ns
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
MR to Qn
tPLH,
tPHL
CL =15pF
CL = 50pF
CL = 50pF
5
-
6
-
-
-
-
-
ns
6
-
-
13
-
16
-
19
ns
2
-
- 170
-
215
-
255
ns
4.5
-
-
34
-
43
-
51
ns
5
-
14
-
-
-
-
-
ns
6
-
-
29
-
37
-
43
ns
Output Transition Time
(Figure 1)
tTLH, tTHL CL = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
Power Dissipation Capaci-
tance
(Notes 3, 4)
CIN
CPD
CL = 50pF
CL =15pF
-
-
-
10
-
10
-
5
-
30
-
-
-
-
10
pF
-
pF
6
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