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CD54HC393_08 Datasheet, PDF (7/15 Pages) Texas Instruments – High-Speed CMOS Logic Dual 4-Stage Binary Counter
◁
CD54HC393, CD74HC393, CD54HCT393, CD74HCT393
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
TEST
VCC
SYMBOL CONDITIONS (V)
25oC
-40oC TO 85oC -55oC TO 125oC
MIN TYP MAX MIN MAX MIN MAX UNITS
HCT TYPES
Propagation Delay Time
(Figure 1)
tPLH,
tPHL
CL = 50pF
nCP to nQ0
CL =15pF
nCP to nQ1
tPLH,
tPHL
CL = 50pF
nCP to nQ2
tPLH,
tPHL
CL = 50pF
nCP to nQ3
tPLH,
tPHL
CL = 50pF
MR to Qn
tPLH,
tPHL
CL = 50pF
CL =15pF
Output Transition
tTLH, tTHL CL = 50pF
Input Capacitance
CIN CL =15pF
Power Dissipation Capacitance
(Notes 3, 4)
CPD
CL =15pF
4.5
-
-
32
-
40
-
48
ns
5
-
13
-
-
-
-
-
ns
4.5
-
-
44
-
55
-
66
ns
4.5
-
-
50
-
63
-
75
ns
4.5
-
-
62
-
78
-
93
ns
4.5
-
-
32
-
40
-
48
ns
5
-
13
-
-
-
-
-
ns
4.5
-
-
15
-
19
-
22
ns
-
-
-
10
-
10
-
10
pF
5
-
21
-
-
-
-
-
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per stage.
4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
tr = 6ns
INPUT
90%
50%
10%
tf = 6ns
VCC
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
50%
10%
tPLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
tr = 6ns
INPUT
tTHL
2.7V
1.3V
0.3V
INVERTING
OUTPUT
tPHL
tf = 6ns
3V
GND
tTLH
90%
1.3V
10%
tPLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
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