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CD54HC393_08 Datasheet, PDF (6/15 Pages) Texas Instruments – High-Speed CMOS Logic Dual 4-Stage Binary Counter
◁
CD54HC393, CD74HC393, CD54HCT393, CD74HCT393
Prerequisite for Switching Specifications (Continued)
25oC
-40oC TO 85oC -55oC TO 125oC
PARAMETER
Reset Recovery Time
SYMBOL VCC (V) MIN
TYP
MAX
MIN
MAX
MIN
MAX UNITS
tREC
2
5
-
-
5
-
5
-
ns
4.5
5
-
-
5
-
5
-
ns
6
5
-
-
5
-
5
-
ns
Reset Pulse Width
tW
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
HCT TYPES
Maximum Clock
Frequency
fMAX
4.5
27
-
-
22
-
18
-
MHz
Clock Pulse Width
Reset Recovery Time
Reset Pulse Width
tW
tREC
tW
4.5
19
-
4.5
5
-
4.5
16
-
-
24
-
29
-
ns
-
5
-
5
-
ns
-
20
-
24
-
ns
Switching Specifications Input tr, tf = 6ns
PARAMETER
TEST
SYMBOL CONDITIONS
VCC
(V)
25oC
-40oC TO 85oC -55oC TO 125oC
MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay Time
(Figure 1)
nCP to nQ0
nCP to nQ1
tPLH,
tPHL
CL = 50pF
tPLH,
tPHL
CL =15pF
CL = 50pF
CL = 50pF
2
-
- 150
-
190
-
225
ns
4.5
-
-
30
-
38
-
59
ns
5
-
12
-
-
-
-
-
ns
6
-
-
26
-
33
-
50
ns
2
-
- 190
-
245
-
295
ns
4.5
-
-
38
-
49
-
59
ns
6
-
-
33
-
42
-
50
ns
nCP to nQ2
tPLH,
tPHL
CL = 50pF
2
-
- 240
-
300
-
360
ns
4.5
-
-
48
-
60
-
72
ns
6
-
-
41
-
51
-
61
ns
nCP to nQ3
tPLH,
tPHL
CL = 50pF
2
-
- 285
-
355
-
430
ns
4.5
-
57
-
71
-
86
ns
6
-
-
48
-
60
-
73
ns
MR to Qn
tPLH,
tPHL
CL = 50pF
2
-
- 135
-
170
-
205
ns
4.5
-
-
27
-
34
-
41
ns
Output Transition Time
(Figure 1)
CL =15pF
CL = 50pF
tTLH, tTHL CL = 50pF
5
-
11
-
-
-
-
-
ns
6
-
-
23
-
29
-
35
ns
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
CIN
CPD
CL = 50pF
CL =15pF
-
-
-
10
-
10
-
10
pF
5
-
20
-
-
-
-
-
pF
6
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