CD54HC109_07 Datasheet, PDF (7/16 Pages) Texas Instruments – Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
Test Circuits and Waveforms
t_rC_L
CLOCK
90%
10%
t_fC_L
50%
10%
t_WL
t_WL
+
t_WH
=
I
f_CL
50%
50%
t_WH
V_CC
GND
t_rC_L = 6ns
CLOCK
2.7V
0.3V
t_fC_L = 6ns
t_WL
+
t_WH
=
I
fC_L
3V
1.3V
0.3V
1.3V
1.3V
GND
t_WL
t_WH
NOTE: Outputs should be switching from 10% V_CC to 90% V_CC in
accordance with device truth table. For f_MAX, input duty cycle = 50%.
FIGURE 7. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V_CC to 90% V_CC in
accordance with device truth table. For f_MAX, input duty cycle = 50%.
FIGURE 8. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t_r = 6ns
INPUT
t_THL
90%
50%
10%
INVERTING
OUTPUT
t_PHL
t_f = 6ns
V_CC
GND
t_TLH
90%
50%
10%
t_PLH
t_r = 6ns
INPUT
t_THL
2.7V
1.3V
0.3V
INVERTING
OUTPUT
t_PHL
t_f = 6ns
3V
GND
t_TLH
90%
1.3V
10%
t_PLH
FIGURE 9. HC AND HCU TRANSITION TIMES AND PROPAGA- FIGURE 10. HCT TRANSITION TIMES AND PROPAGATION
TION DELAY TIMES, COMBINATION LOGIC
DELAY TIMES, COMBINATION LOGIC
t_rC_L
CLOCK
INPUT
DATA
INPUT
t_SU(H)
90%
10%
t_H(H)
t_fC_L
50%
t_H(L)
t_SU(L)
V_CC
GND
V_CC
50%
GND
t_rC_L
CLOCK
INPUT
2.7V
0.3V
t_fC_L
1.3V
t_H(H)
t_H(L)
DATA
INPUT
t_SU(H)
1.3V
1.3V
1.3V
t_SU(L)
3V
GND
3V
GND
OUTPUT
t_REM
V_CC
SET, RESET
OR PRESET
t_TLH
90%
t_PLH
50%
t_THL
90%
50%
10%
t_PHL
GND
OUTPUT
t_REM
3V
SET, RESET
OR PRESET
t_TLH
90%
1.3V
t_PLH
1.3V
t_THL
90%
1.3V
10%
t_PHL
GND
IC
C_L
50pF
IC
C_L
50pF
FIGURE 11. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 12. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
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