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CD54HC109_07 Datasheet, PDF (6/16 Pages) Texas Instruments – Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger
◁
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
TEST
VCC
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Propagation Delay,
R→Q
tPLH, tPHL CL = 50pF
2
-
- 185
-
230
-
280
ns
CL = 50pF
4.5 -
-
37
-
46
-
56
ns
CL = 15pF
5
- 15 -
-
-
-
-
ns
CL = 50pF
6
-
- 31
-
39
-
48
ns
Propagation Delay,
R→Q
tPLH, tPHL CL = 50pF
2
-
- 170
-
215
-
255
ns
CL = 50pF
4.5 -
-
34
-
43
-
51
ns
CL = 15pF
5
- 14 -
-
-
-
-
ns
CL = 50pF
6
-
- 29
-
37
-
43
ns
Transition Time
tTLH, tTHL CL = 50pF
2
-
- 75
-
95
-
110
ns
CL = 50pF
4.5 -
-
15
-
19
-
22
ns
CL = 50pF
6
-
- 13
-
16
-
19
ns
Input Capacitance
CI
-
-
-
-
10
-
10
-
10
pF
CP Frequency
fMAX CL = 15pF
5
- 60 -
-
-
-
-
MHz
Power Dissipation Capacitance
(Notes 4, 5)
CPD
-
5
- 30 -
-
-
-
-
pF
HCT TYPES
Propagation Delay,
CP → Q, Q
tPLH, tPHL CL = 50pF
4.5 -
-
40
-
50
-
60
ns
CL = 15pF
5
- 17 -
-
-
-
-
ns
Propagation Delay,
S→Q
tPLH, tPHL CL = 50pF
4.5 -
-
30
-
38
-
45
ns
CL = 15pF
5
- 12 -
-
-
-
-
ns
Propagation Delay,
S→Q
tPLH, tPHL CL = 50pF
4.5 -
-
45
-
56
-
68
ns
CL = 15pF
5
- 19 -
-
-
-
-
ns
Propagation Delay,
R→Q
tPLH, tPHL CL = 50pF
4.5 -
-
45
-
56
-
68
ns
CL = 15pF
5
- 19 -
-
-
-
-
ns
Propagation Delay,
R→Q
tPLH, tPHL CL = 50pF
4.5 -
-
37
-
46
-
56
ns
CL = 15pF
5
- 15 -
-
-
-
-
ns
Transition Time (Figure 5)
tTLH, tTHL CL = 50pF
4.5 -
-
15
-
19
-
22
ns
Input Capacitance
CI
-
-
-
-
10
-
10
-
10
pF
CP Frequency
fMAX
CL = 15pF
5
- 54 -
-
-
-
-
MHz
Power Dissipation Capacitance
(Notes 4, 5)
CPD
-
5
- 33 -
-
-
-
-
pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per flip-flop.
5. PD = CPD VCC2 fi + Σ CL fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
6
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