BQ4015_07 Datasheet, PDF (7/15 Pages) Texas Instruments – 512Kx8 Nonvolatile SRAM

bq4015/Y
Write Cycle (TA = TOPR, VCCmin ≤ VCC ≤ VCCmax)
Symbol
Parameter
tWC
Write cycle time
tCW
Chip enable to end of write
tAW
Address valid to end of write
tAS
Address setup time
tWP
Write pulse width
tWR1
Write recovery time
(write cycle 1)
tWR2
Write recovery time
(write cycle 2)
tDW
Data valid to end of write
tDH1
tDH2
tWZ
tOW
Data hold time
(write cycle 1)
Data hold time
(write cycle 2)
Write enabled to output in
high Z
Output active from end of
write
-70
-85/-85N -120/-120N
Min. Max. Min. Max. Min. Max. Units Conditions/Notes
70 - 85 - 120 -
ns
65 - 75 - 100 -
ns
(1)
65 - 75 - 100 -
ns
(1)
Measured from address
0
-
0
-
0
-
ns valid to beginning of
write. (2)
55 - 65 - 85 -
Measured from begin-
ns ning of write to end of
write. (1)
Measured from WE go-
5
-
5
-
5
-
ns ing high to end of write
cycle. (3)
15 - 15 - 15 -
Measured from CE going
ns high to end of write cy-
cle. (3)
30 - 35 - 45 -
Measured to first low-
ns to-high transition of ei-
ther CE or WE.
Measured from WE go-
0
-
0
-
0
-
ns ing high to end of write
cycle. (4)
10 - 10 - 10 -
Measured from CE going
ns high to end of write cy-
cle. (4)
0
25
0
30
0
40
ns
I/O pins are in output
state. (5)
5
-
0
-
0
-
ns
I/O pins are in output
state. (5)
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
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