BQ26231 Datasheet, PDF (7/18 Pages) Texas Instruments – LOW COST BATTERY COULOMB COUNTER FOR EMBEDDED PORTABLE APPLICATIONS

bq26231
APPLICATION INFORMATION
SLUS491 – JULY 2001
functional description (continued)
charge and discharge count operation
Table 2 shows the main counters and registers of the bq26231. The bq26231 accumulates charge and
discharge counts into two main count registers the discharge count register (DCR) and the charge count register
(CCR). The bq26231 produces charge and discharge counts by sensing the voltage difference across a
low-value resistor between the negative terminal of the battery pack and the negative terminal of the battery.
The DCR or CCR counts depending on the signal between SR1 and SR2.
Table 2. bq26231 Counters
NAME
DCR
CCR
SCR
DTC
DESCRIPTION
Discharge count register
Charge count register
Self-discharge count register
Discharge time counter
CTC Charge time counter
RANGE
V(SR1) < V(SR2) (max = –200 mV) 12.5 µV increments
V(SR1) > V(SR2) (max = +200 mV) 12.5 µV increments
1 count/hour at 25°C
1 count/0.8789 s (default)
1 count/225 s if STD is set
1 count/0.8789 s (default)
1 count/225 s if STC is set
RAM SIZE
16 bit
16 bit
16 bit
16 bit
16 bit
During discharge, the DCR and the discharge time counter (DTC) are active. If V_(SR1) is less than V_(SR2),
indicating a discharge, the DCR counts at a rate equivalent to 12.5 µV every hour, and the DTC counts at a rate
of 1 count/0.8789 seconds (4096 counts per hour). For example, a –100 mV signal produces 8000 DCR counts
and 4096 DTC counts each hour. The amount of charge removed from the battery is easily calculated.
During charge, the CCR and the charge time counter (CTC) are active. If V_(SR1) is greater than V_(SR2), indicating
a charge, the CCR counts at a rate equivalent to 12.5 µV every hour, and the CTC counts at a rate of 1
count/0.8789 seconds. For example, a +100 mV signal produces 8000 CCR counts and 4096 CTC counts each
hour. The amount of charge added to the battery can easily be calculated.
The DTC and the CTC are 16-bit registers, and roll over beyond FFFF hex. If a rollover occurs, the
corresponding bit in the MODE/WOE register is set, and the counter will subsequently increment at 1/256 of
the normal rate (16 counts/hr). Whenever the signal between SR1 and SR2 is above the wake-up output enable
(WOE) threshold and the HDQ pin is high, the bq26231 is in its full operating state. In this state, the DCR, CCR,
DTC, CTC, and SCR are fully operational, and the WAKE output is low. During this mode, the internal RAM
registers of the bq26231 may be accessed over the HDQ pin, as described in the section Communicating With
the 26230.
If the signal between SR1 and SR2 is below the WOE threshold (refer to the Mode/Wake-Up Enable Register
section for details) and HDQ remains low for greater than 10 seconds, the bq26231 enters a sleep mode where
all register counting is suspended. The bq26231 remains in this mode until HDQ returns high.
For self-discharge calculation, the self-discharge count register (SCR) counts at a rate equivalent to 1 count
every hour at a nominal 25°C. This rate and doubles approximately every 10°C up to 60°C. The SCR count rate
is halved every 10°C below 25°C down to 0°C. The value in SCR is useful in determining an estimation of the
battery self-discharge based on capacity and storage temperature conditions.
At any time during pack assembly, by invoking the calibration mode, the bq26231 may be programmed to
measure the voltage offset between SR1 and SR2. The offset register (OFR) stores the bq26231 offset. The
bit 2s complement value stored in the OFR is scaled the same units as the DCR and CCR, representing the
amount of positive or negative offset in the bq26231. The maximum offset for the bq26231 is specified as ± 500
µV. Care should be taken to ensure proper PCB layout. Using OFR, the system host can cancel most of the
effects of bq26231 offset for greater resolution and accuracy.
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