BQ26231 Datasheet, PDF (12/18 Pages) Texas Instruments – LOW COST BATTERY COULOMB COUNTER FOR EMBEDDED PORTABLE APPLICATIONS

bq26231
SLUS491 – JULY 2001
APPLICATION INFORMATION
command (CMDR) (continued)
The lower seven-bit field of CMDR contains the address portion of the register to be accessed.
CDMR BITS
7
6
5
4
3
2
1
0
–
AD6
AD5
AD4
AD3
AD2
AD1
AD0
discharge count registers (DCRH/DCRL)
The DCRH high-byte register (address = 7F hex) and the DCRL low-byte register (address = 7E hex) contain
the count of the discharge and are incremented whenever V_(SR1) < V_(SR2). These registers continue to count
beyond FFFF hex, so proper register maintenance should be done by the host system. The TMP/CLR register
is used to force the reset of both the DCRH and DCRL to zero.
charge count registers (CCRH/CCRL)
The CCRH high-byte register (address = 7D hex) and the CCRL low-byte register (address = 7C hex) contain
the count of the charge, and are incremented whenever V_(SR1) > V_(SR2). These registers continue to count
beyond FFFF hex, so proper register maintenance should be done by the host system. The TMP/CLR register
is used to force the reset of both the CCRH and CCRL to zero.
self-discharge count registers (SCRH/SCRL)
The SCRH high-byte register (address = 7B hex) and the SCRL low-byte register (address = 7A hex) contain
the self-discharge count. These registers are continually updated when the bq26231 is in its normal operating
mode. The counts in these registers are incremented based on time and temperature. The SCR counts at a rate
of 1 count per hour at 20–30°C and doubles every 10°C to greater than 60°C (16 counts/hour). The count will
halve every 10°C below 20–30°C to less than 0°C (1 count/8 hours). These registers continue to count beyond
FFFF hex, so proper register maintenance should be done by the host system. The TMP/CLR register is used
to force the reset of both the SCRH and SCRL to zero.
discharge time count registers (DTCH/DTCL)
The DTCH high-byte register (address = 79 hex) and the DTCL low-byte register (address = 78 hex) are used
to determine the length of time the V_(SR1) < V_(SR2), indicating a discharge. The counts in these registers are
incremented at a rate of 4096 counts per hour. If the DTCH/DTCL register continues to count beyond FFFF hex,
the STD bit is set in the MODE/WOE register, indicating a rollover. Once set, DTCH and DTCL increment at a
rate of 16 counts per hour. The TMP/CLR register is used to force the reset of both the DTCH and DTCL to zero.
NOTE:
If a second rollover occurs, STD is cleared. Access to the bq26231 should be timed to clear
DTCH/DTCL more often than every 170 days.
charge time count registers (CTCH/CTCL)
The CTCH high-byte register (address = 77 hex) and the CTCL low-byte register (address = 76 hex) are used
to determine the length of time the V_(SR1) > V_(SR2), indicating a charge. The counts in these registers are
incremented at a rate of 4096 counts per hour. If the CTCH/CTCL registers continue to count beyond FFFF hex,
the STC bit is set in the MODE/WOE register, indicating a rollover. Once set, DTCH and DTCL increment at a
rate of 16 counts per hour. The TMP/CLR register is used to force the reset of both the CTCH and CTCL to zero.
NOTE:
If a second rollover occurs, STD is cleared. Access to the bq26231 should be timed to clear
CTCH/CTCL more often than every 170 days.
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