BQ24180_1 Datasheet, PDF (7/41 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and Accessory Power Connection

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PIN CONFIGURATION
A
bq24180
SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010
DEVICE INFORMATION
TOP VIEW
1
2
3
4
5
VBUS
VBUS
BOOT
SCL
SDA
B
PMID
PMID
PMID
INT
CD
C
SW
SW
SW
PSEL
STAT
D
PGND
PGND
PGND
DCOUT DCOUT
E
CSIN
TS
DRV
CSOUT CSOUT
2.2 mm x 2.4 mm 25-pin WCSP
PIN FUNCTIONS
NAME PIN NO. I/O
DESCRIPTION
VBUS A1, A2
I/O Charger Input Voltage. Connect to an input supply up to 16V. Bypass VBUS to PGND with a 1µF ceramic
capacitor.
BOOT A3
SCL A4
SDA A5
O High-Side MOSFET Gate Driver Supply. Connect a 10nF ceramic capacitor (voltage rating above 10V) from
BOOT pin to SW pin to supply the gate drive for the high side MOSFET.
I I²C interface clock. Connect SCL to the logic rail through a 10kΩ resistor.
I/O I²C interface data. Connect SCL to the logic rail through a 10kΩ resistor.
PMID
B1, B2, B3 O Connection Point Between Reverse Blocking MOSFET and High-Side Switching MOSFET. Bypass PMID to
PGND with a minimum of 3.3µF ceramic capacitor. Use caution when connecting an external load to PMID.
The PMID output is not current limited. Any short on PMID will result in damage to the IC.
INT
B4
O Host Interface Status Output. INT is a low voltage open drain output used to signal charge status to the host
processor. INT is pulled low during charging. When charging is complete or when charging is disabled, INT is
high impedance. When a fault occurs, a 128µs pulse is sent out as an interrupt for the host. INT is
enabled/disabled using the EN_STAT bit in the control register. Connect INT to a logic rail through a 10kΩ
resistor to communicate with the host processor.
CD
B5
O Hardware Disable Input. Connect CD to GND to enable charge. Drive CD high to disable charge and place
the bq24180 into high impedance mode. Toggling CD resets the safety timer when in DEFAULT mode, but
does not reset the timer when in host mode. CD is pulled to PGND through a 100kΩ internal resistor.
SW
C1, C2,
C3
O Inductor Connection. Connect the switched side of the inductor to SW.
PSEL C4
I USB Source Detection Input. Drive PSEL high to indicate a USB source is connected to the input and the PC
mode default values should be used. When PSEL is high, the IC starts up with a 100mA input current limit.
Drive PSEL low to indicate that an AC Adapter is connected to the input. When PSEL is low, the IC starts up
with no input current limit and a 1A charge current. PSEL has an internal 100kΩ pullup resistor.
STAT C5
O Status Output. STAT is an open drain output that is pulled low during charging. When charging is complete or
when charging is disabled, STAT is high impedance. When a fault occurs, a 128µs pulse is sent out as an
interrupt for the host. STAT is enabled/disabled using the EN_STAT bit in the control register. Connect STAT
to a logic rail using an LED for visual indication or through a 10kΩ resistor to communicate with the host
processor.
PGND D1, D2,
D3
Power ground. Connect to the ground plane for the circuit.
DCOUT D4, D5
O Accessory Power Output. DCOUT is connected to the battery through an internal pass FET. When enabled
through I2C, DCOUT is connected to the battery. When disabled, DCOUT is high-impedance. Bypass DCOUT
to PGND with at least a 1µF ceramic capacitor.
CSIN E1
I Charge Current-Sense Input. Battery current is sensed via the voltage drop across an external sense resistor.
Bypass CSIN to PGND with a 0.1µF ceramic capacitor.
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq24180
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