BQ24180_1 Datasheet, PDF (25/41 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and Accessory Power Connection

bq24180
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SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010
SERIAL INTERFACE DESCRIPTION
I²C is a 2-wire serial interface developed by Philips Semiconductor (see I²C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus
through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The bq24180 device works as a slave and is compatible with the following data transfer modes, as defined in the
I²C Bus™ Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps
in write mode). The interface adds flexibility to the battery charge solution, enabling most functions to be
programmed to new values depending on the instantaneous application requirements. Register contents remain
intact as long as battery voltage remains above 2.5 V (typical). The I²C circuitry is powered from VBUS when a
supply is connected. If the VBUS supply is not connected, the I²C circuitry is powered from the battery through
CSOUT. The battery voltage must stay above 2.5V with no input connected in order to maintain proper operation.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to
as the HS-mode. The bq24150/1 device only supports 7-bit addressing. The device 7-bit address is defined as
‘1101011’ (6BH).
F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 33. All I2C -compatible devices should
recognize a start condition.
DATA
CLK
START Condition
STOP Condition
Figure 33. START and STOP Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 34). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 34) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Charge
of Data
Allowed
Figure 34. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
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