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BQ20Z80-V102 Datasheet, PDF (7/24 Pages) Texas Instruments – SBS 1.1-COMPLIANT GAS GAUGE ENABLED WITH IMPEDANCE TRACK-TM TECHNOLOGY FOR USE WITH THE bq29312A
bq20z80-V102
www.ti.com
SLUS681A – NOVEMBER 2005 – REVISED MARCH 2006
SMBus TIMING SPECIFICATIONS
VDD = 3 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fSMB
fMAS
tBUF
tHD:STA
tSU:STA
tSU:STO
tHD:DAT
SMBus operating frequency
SMBus master clock frequency
Bus free time between start and stop
Hold time after (repeated) start
Repeated start setup time
Stop setup time
Data hold time
Slave mode, SMBC 50% duty cycle
Master mode, no clock low slave extend
Receive mode
Transmit mode
tSU:DAT
tTIMEOUT
tLOW
tHIGH
tLOW:SEXT
tLOW:MEXT
tF
tR
Data setup time
Error signal/detect
Clock low period
Clock high period
Cumulative clock low slave extend time
Cumulative clock low master extend time
Clock/data fall time
Clock/data rise time
See (1)
See (2)
See (3)
See (4)
(VILMAX– 0.15 V) to (VIHMIN + 0.15 V)
0.9 VDD to (VILMAX – 0.15 V)
MIN TYP MAX UNIT
10
51.2
100
kHz
4.7
4
µs
4.7
4
0
300
ns
250
25
35 ms
4.7
µs
4
50
25
ms
10
300
ns
1000
(1) The bq20z80 times out when any clock low exceeds tTIMEOUT.
(2) tHIGH:MAX. is minimum bus idle time. SMBC = 1 for t > 50 µs causes reset of any transaction involving the bq20z80 that is in progress.
(3) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
SMBus TIMING DIAGRAM
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