BQ20Z75DBTR-V180 Datasheet, PDF (7/23 Pages) Texas Instruments – SBS 1.1-COMPLIANT GAS GAUGE AND PROTECTION-ENABLED IC WITH IMPEDANCE TRACK

bq20z75-V180
www.ti.com
SLUSA22 – DECEMBER 2009
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted), T_A = –40°C to 85°C, V_REG25 = 2.41 V to 2.59 V, V_BAT =
14V, C_REG25 = 1µF, C_REG33 = 2.2µF; typical values at T_A = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
I_{VCELL+OU Drive Current to VCELL+ capacitor}
T
V_VCELL+O CELL offset error
VC(n) – VC(n+1) = 0V; VCELL+ =
0V; T_A = –40°C to 100°C
CELL output (VC2 = VC1 = 18V) –
CELL output (VC2 = VC1 = 0V)
12
18
μA
–18
–1
18 mV
I_VCnL
VC(n) pin leakage current
CELL BALANCING
VC1, VC2, VC3, VC4, VC5 = 3V
–1
0.01
1 μA
R_BAL
internal cell balancing FET resistance
R_DS(on) for internal FET switch at V_DS
= 2V; T_A = 25°C
200
HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; T_A = 25°C (unless otherwise noted)
V_OL = 25mV (min)
15
V_(OL)
OL detection threshold voltage accuracy V_OL = 100mV; RSNS = 0, 1
90
V_OL = 205mV (max)
185
V_SCC = 50mV (min)
30
V_(SCC)
SCC detection threshold voltage
accuracy
V_SCC = 200mV; RSNS = 0, 1
180
V_SCC = 475mV (max)
428
V_(SCD)
SCD detection threshold voltage
accuracy
V_SCD = –50mV (min)
V_SCD = –200mV; RSNS = 0, 1
V_SCD = –475mV (max)
–30
–180
–428
t_da
Delay time accuracy
t_pd
Protection circuit propagation delay
FET DRIVE CIRCUIT; T_A = 25°C (unless otherwise noted)
V_DSGON = V_DSG – V_PACK; V_GS =
V_DSGON DSG pin output on voltage
10MΩ;DSG and CHG on; T_A =
8
–40°C to 100°C
400
25
100
205
50
200
475
–50
–200
–475
±15.25
50
12
600 Ω
35
110 mV
225
70
220 mV
523
–70
–220 mV
–523
μs
μs
16 V
V_CHGON CHG pin output on voltage
V_CHGON = V_CHG – V_BAT; V_GS =
10MΩ;DSG and CHG on; T_A =
–40°C to 100°C
8
12
16 V
V_DSGOFF DSG pin output off voltage
V_DSGOFF = V_DSG – V_PACK
V_CHGOFF CHG pin output off voltage
V_CHGOFF = V_CHG – V_BAT
t_R
Rise time
C_L=4700pF; V_PACK ≤ DSG ≤V_PACK +
4V
C_L=4700pF; V_BAT ≤ CHG ≤V_BAT + 4V
t_F
Fall time
C_L=4700pF; V_PACK + V_DSGON ≤ DSG
≤V_PACK + 1V
C_L=4700pF; V_BAT + V_CHGON ≤ CHG
≤V_BAT + 1V
V_ZVCHG ZVCHG clamp voltage
BAT = 4.5V
LOGIC; T_A = –40°C to 100°C (unless otherwise noted)
ALERT
60
R_PULLUP Internal pullup resistance
RESET
1
0.2 V
0.2 V
400
1000
μs
400
1000
40
200
μs
40
200
3.3
3.5
3.7 V
100
200
kΩ
3
6
ALERT
0.2
V_OL
Logic low output voltage level
LOGIC SMBC, SMBD, PFIN, PRES, SAFE, ALERT
RESET; V_BAT = 7V; V_REG25 = 1.5V; I
RESET ^{= 200μA}
GPOD; I_GPOD = 50μA
0.4
V
0.6
V_IH
High-level input voltage
V_IL
Low-level input voltage
2.0
V
0.8 V
Copyright © 2009, Texas Instruments Incorporated
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