BQ20Z75DBTR-V180 Datasheet, PDF (3/23 Pages) Texas Instruments – SBS 1.1-COMPLIANT GAS GAUGE AND PROTECTION-ENABLED IC WITH IMPEDANCE TRACK

bq20z75-V180
www.ti.com
TERMINAL
NO.
NAME
1
DSG
2
PACK
3
VCC
4
ZVCHG
5
GPOD
6
PMS
7
VSS
8
REG33
9
TOUT
10
VCELL+
11
ALERT
12
PRES
13
TS1
14
TS2
15
PFIN
16
SAFE
17
SMBD
18
SMBC
19
NC
20
VSS
21
VSS
22
GSRP
23
GSRN
24
MRST
25
VSS
26
REG25
27
RBI
28
VSS
29
RESET
30
ASRN
31
ASRP
32
VC5
33
VC4
34
VC3
35
VC2
36
VC1
SLUSA22 – DECEMBER 2009
TERMINAL FUNCTIONS
I/O ⁽¹⁾
DESCRIPTION
O
IA, P
P
O
OD
I
P
P
P
-
I/OD
I/OD
IA
IA
I/OD
I/OD
I/OD
I/OD
-
P
P
IA
IA
I
P
P
P
P
O
IA
IA
IA,P
IA,P
IA,P
IA,P
IA,P
High side N-channel discharge FET gate drive
Battery pack input voltage sense input. It also serves as device wake up when device is in shutdown
mode.
Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to
ensure device supply either from battery stack or battery pack input
P-channel pre-charge FET gate drive
High voltage general purpose open drain output. Can be configured to be used in pre-charge
condition
Pre-charge mode setting input. Connect to PACK to enable 0v pre-charge using charge FET
connected at CHG pin. Connect to VSS to disable 0V pre-charge using charge FET connected at
CHG pin.
Negative device power supply input. Connect all VSS pins together for operation of device
3.3V regulator output. Connect at least a 2.2μF capacitor to REG33 and VSS
Termistor bias supply output
Internal cell voltage multiplexer and amplifier output. Connect a 0.1μF capacitor to VCELL+ and VSS
Alert output. In case of short circuit condition, overload condition and watchdog time out this pin will
be triggered.
System / Host present input. Pull up to TOUT
Temperature sensor 1 input
Temperature sensor 2 input
Fuse blow detection input
blow fuse signal output
SMBus data line
SMBus clock line
Not Connected
Negative device power supply input. Connect all VSS pins together for operation of device.
Negative device power supply input. Connect all VSS pins together for operation of device.
Coulomb counter differential input. Connect to one side of the sense resistor
Coulomb counter differential input. Connect to one side of the sense resistor
Reset input for internal CPU core. connect to RESET for correct operation of device.
Negative device power supply input. Connect all VSS pins together for operation of device.
2.5V regulator output. Connect at least a 1μF capacitor to REG25 and VSS
RAM backup input. Connect a capacitor to this pin and VSS to protect loss of RAM data in case of
short-circuit condition
Negative device power supply input. Connect all VSS pins together for operation of device
Reset output. Connect to MSRT.
Short-circuit and overload detection differential input
Short-circuit and overload detection differential input
Cell voltage sense input and cell balancing input for the negative voltage of the bottom cell in cell
stack.
Cell voltage sense input and cell balancing input for the positive voltage of the bottom cell and the
negative voltage of the second lowest cell in cell stack.
Cell voltage sense input and cell balancing input for the positive voltage of the second lowest cell in
cell stack and the negative voltage of the second highest cell in 4 cell applications.
Cell voltage sense input and cell balancing input for the positive voltage of the second highest cell
and the negative voltage of the highest cell in 4 cell applications. Connect to VC3 in 2 cell stack
applications
Cell voltage sense input and cell balancing input for the positive voltage of the highest cell in cell
stack in 4 cell applications. Connect to VC2 in 3 or 2 cell stack applications
(1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power
Copyright © 2009, Texas Instruments Incorporated
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