ADS8329 Datasheet, PDF (7/40 Pages) Texas Instruments – LOW POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE

www.ti.com
ADS8329
ADS8330
SLAS516 – DECEMBER 2006
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V ⁽¹⁾⁽²⁾
f_CCLK
t_su(CSF-EOC)
t_h(CSF-EOC)
t_wL(CONVST)
t_su(CSF-EOS)
t_h(CSF-EOS)
t_su(CSR-EOS)
t_h(CSR-EOS)
t_{su(CSF-SCLK1R)}
t_wL(SCLK)
t_wH(SCLK)
t_c(SCLK)
t_{d(SCLKF-SDOINVALID)}
t_{d(SCLKF-SDOVALID)}
t_{d(CSF-SDOVALID)}
t_{su(SDI-SCLKF)}
t_h(SDI-SCLKF)
t_d(CSR-SDOZ)
t_{su(lastSCLKF-CSR)}
t_d(SDO-CDI)
PARAMETER
Frequency, conversion clock, CCLK,
f_CCLK = 1/2 f_SCLK
Setup time, falling edge of CS to EOC
Hold time, falling edge of CS to EOC
Pulse duration, CONVST low
Setup time, falling edge of CS to EOS
Hold time, falling edge of CS to EOS
Setup time, rising edge of CS to EOS
Hold time, rising edge of CS to EOS
Setup time, falling edge of CS to SCLK
Pulse duration, SCLK low
Pulse duration, SCLK high
Cycle time, SCLK
Delay time, falling edge of SCLK to SDO
invalid
Delay time, falling edge of SCLK to SDO
valid
Delay time, falling edge of CS to SDO
valid, SDO MSB output
Setup time, SDI to falling edge of SCLK
Hold time, SDI to falling edge of SCLK
Delay time, rising edge of CS/FS to SDO
3-state
Setup time, last falling edge of SCLK
before rising edge of CS/FS
Delay time, CDI high to SDO high in daisy
chain mode
External
Internal
I/O Clock only
I/O and conversion clock
I/O Clock, chain mode
I/O and conversion clock,
chain mode
10-pF Load
10-pF Load
10-pF Load
10-pF Load, chain mode
MIN
0.5
21
1
0
40
20
20
20
20
5
8
8
20
23.8
20
23.8
TYP
22.9
MAX UNIT
21 MHz
24.5
CCLK
ns
ns
ns
ns
ns
ns
t_c(SCLK) - 5 ns
t_c(SCLK) - 8 ns
t_c(SCLK) - 8 ns
2000
ns
2000
5
ns
12 ns
12 ns
8
ns
4
ns
5 ns
10
ns
16 ns
(1) All input signals are specified with t_r = t_f = 1.5 ns (10% to 90% of V_DD) and timed from a voltage level of (V_IL + V_IH)/2.
(2) See timing diagrams.
Submit Documentation Feedback
7