ADS8329 Datasheet, PDF (24/40 Pages) Texas Instruments – LOW POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE

ADS8329
ADS8330
SLAS516 – DECEMBER 2006
www.ti.com
THEORY OF OPERATION (continued)
The duty cycle of SCLK is not critical as long as it meets the minimum high and low time requirements of 8 ns.
Since the ADS8329/30 is designed for high-speed applications, a higher serial clock (SCLK) must be supplied to
be able to sustain the high throughput with the serial interface and so the clock period of SCLK must be at most
1 µs (when used as conversion clock (CCLK). The minimum clock frequency is also governed by the parasitic
leakage of the capacitive digital-to-analog (CDAC) capacitors internal to the ADS8329/30.
CFR_D10
Conversion Clock
=1
(CCLK)
=0
OSC
Divider
1/2
SPI Serial
Clock (SCLK)
Figure 54. Converter Clock
Manual Channel Select Mode
The conversion cycle starts with selecting an acquisition channel by writing a channel number to the command
register (CMR). This cycle time can be as short as 4 serial clocks (SCLK).
Auto Channel Select Mode
Channel selection can also be done automatically if auto channel select mode is enabled. This is the default
channel select mode. The dual channel converter, ADS8330, has a built-in 2-to-1 MUX. If the device is
programmed for auto channel select mode then signals from channel 0 and channel 1 are acquired with a fixed
order. Channel 0 is accessed first in the next cycle after the command cycle that configured CFR_D11 to 1 for
auto channel select mode. This automatic access stops the cycle after the command cycle that sets CFR_D11
to 0.
Start of a Conversion
The end of acquisition or sampling instance (EOS) is the same as the start of a conversion. This is initiated by
bringing the CONVST pin low for a minimum of 40 ns. After the minimum requirement has been met, the
CONVST pin can be brought high. CONVST acts independent of FS/CS so it is possible to use one common
CONVST for applications requiring simultaneous sample/hold with multiple converters. The ADS8329/30
switches from sample to hold mode on the falling edge of the CONVST signal. The ADS8329/30 requires 18
conversion clock (CCLK) edges to complete a conversion. The conversion time is equivalent to 1500 ns with a
12-MHz internal clock. The minimum time between two consecutive CONVST signals is 21 CCLKs.
A conversion can also be initiated without using CONVST if it is so programmed (CFR_D9 = 0). When the
converter is configured as auto trigger, the next conversion is automatically started 3 conversion clocks (CCLK)
after the end of a conversion. These 3 conversion clocks (CCLK) are used as the acquisition time. In this case
the time to complete one acquisition and conversion cycle is 21 CCLKs.
Table 1. Different Types of Conversion
MODE
SELECT CHANNEL
Auto Channel Select⁽¹⁾
Automatic _{No need to write channel number to the CMR. Use internal sequencer for the}
ADS8330.
Manual
Manual Channel Select
Write the channel number to the CMR.
START CONVERSION
Auto Trigger
Start a conversion based on the
conversion clock CCLK.
Manual Trigger
Start a conversion with CONVST.
(1) Auto channel select should be used with auto trigger and also with the TAG bit enabled.
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