TMS320VC5410 Datasheet, PDF (67/79 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

TMS320VC5410
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
multichannel buffered serial port timing (continued)
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
timing requirements for McBSP as SPI master or slave: [H=0.5t_c(CO)] CLKSTP = 11b, CLKXP = 0^†
(see Figure 37)
’5410-100
’5410-120
MASTER
SLAVE
MASTER
SLAVE
MIN MAX
MIN MAX
MIN MAX
MIN MAX
tsu(BDRV-BCKXL)
Setup time, BDR valid
before BCLKX low
12
7 – 6H
12
7 – 6H
th(BCKXH-BDRV)
Hold time, BDR valid
after BCLKX high
0
5 + 6H
0
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
5 + 6H
UNIT
ns
ns
switching characteristics for McBSP as SPI master or slave: [H=0.5t_c(CO)] CLKSTP = 11b,
CLKXP = 0^† (see Figure 37)
PARAMETER
’5410-100
MASTER^‡
SLAVE
’5410-120
MASTER^‡
SLAVE
UNIT
MIN MAX
MIN
MAX MIN MAX
MIN
MAX
th(BCKXL-BFXL)
Hold time, BFSX low after
BCLKX low§
C–7 C+4
C–7 C+4
ns
td(BFXL-BCKXH)
Delay time, BFSX low to
BCLKX high¶
T –7 T + 5
T –7 T + 5
ns
td(BCKXL-BDXV)
Delay time, BCLKX low to
BDX valid
–3
4 6H + 4 10H + 15 – 3
4 6H + 4 10H + 15 ns
Disable time, BDX high
tdis(BCKXL-BDXHZ) impedance following last
data bit from BCLKX low
–2
4 6H + 3 10H + 17
–2
4 6H + 3 10H + 17 ns
td(BFXL-BDXV)
Delay time, BFSX low to
BDX valid
D – 3 D + 5 4H + 2 8H + 17 D – 3 D + 5 4H + 2 8H + 17 ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{T = BCLKX period = (1 + CLKGDV) * 2H}
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ _{FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX}
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ _{BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(BCLKX).
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