TMS320VC5410 Datasheet, PDF (1/79 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

TMS320VC5410
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
D Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
D 40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
D 17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
D Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
D Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
D Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D Data Bus With a Bus Holder Feature
D Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space
D 64K x 16-Bit On-Chip RAM Composed of:
– Four Blocks of 2K × 16-Bit On-Chip
Dual-Access Program/Data RAM
– Seven Blocks of 8K × 16-Bit On-Chip
Single-Access Program/Data RAM
D 16K × 16-Bit On-Chip ROM Configured to
Program Memory
D Enhanced External Parallel Interface (XIO2)
D Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
D Block-Memory-Move Instructions for Better
Program and Data Management
D Instructions With a 32-Bit Long Word
Operand
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
D Instructions With Two- or Three-Operand
Reads
D Arithmetic Instructions With Parallel Store
and Parallel Load
D Conditional Store Instructions
D Fast Return From Interrupt
D On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable
Bank-Switching
– On-Chip Programmable Phase-Locked
Loop (PLL) Clock Generator With
Internal Oscillator or External Clock
Source
– One 16-Bit Timer
– Six-Channel Direct Memory Access
(DMA) Controller
– Three Multichannel Buffered Serial Ports
(McBSPs)
– 8-Bit Enhanced Parallel Host-Port
Interface (HPI8)
D Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
D CLKOUT Off Control to Disable CLKOUT
D On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1^† (JTAG) Boundary Scan
Logic
D 144-Pin Thin Quad Flatpack (TQFP)
(PGE Suffix)
D 176-Pin Ball Grid Array (BGA)
(GGW Suffix)
D 10-ns and 8.3-ns Single-Cycle Fixed-Point
Instruction Execution Time (100 and 120
MIPS)
D 3.3-V I/O and 2.5-V Core Supply Voltages
description
The TMS320VC5410 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’5410 unless
otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus
and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of
parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis
of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† _{IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.}
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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