TMS320C6211 Datasheet, PDF (67/87 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6211, TMS320C6211B
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SPRS073L − AUGUST 1998 − REVISED JUNE 2004
HOST-PORT INTERFACE TIMING (CONTINUED)
HAS
1
HCNTL[1:0]
1
HR/W
1
HHWIL
HSTROBE†
2
2
2
3
1
2
1
2
1
2
4
3
HCS
15
15
7
9
16
9
HD[15:0] (output)
5
HRDY (case 1)
1st halfword
8
2nd halfword
17
5
6
8
HRDY (case 2)
5
17
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
Figure 33. HPI Read Timing (HAS Not Used, Tied High)
HAS†
19
10
11
HCNTL[1:0]
19
10
11
10
HR/W
10
HHWIL
HSTROBE‡
HCS
11
11
3
18
11
10
11
10
4
18
15
15
7
9
16
9
HD[15:0] (output)
5
1st half-word
8
2nd half-word
17
5
HRDY (case 1)
20
8
17
5
HRDY (case 2)
† _{For correct operation, strobe the HAS signal only once per HSTROBE active cycle.}
‡ _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
Figure 34. HPI Read Timing (HAS Used)
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