TMS320C6211 Datasheet, PDF (35/87 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

clock PLL (continued)
3.3V
PLLV
CLKMODE0
CLKIN
TMS320C6211, TMS320C6211B
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SPRS073L − AUGUST 1998 − REVISED JUNE 2005
PLLMULT
PLL
PLLCLK
CLKIN
LOOP FILTER
Internal to
C6211/C6211B
1
CPU
0
CLOCK
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal.
B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 6. External PLL Circuitry for x1 (Bypass) Mode Only
Table 18. C6211/C6211B PLL Component Selection
CLKMODE
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
(CLKOUT1)
RANGE (MHz)
CLKOUT2
RANGE
(MHz)
R1 [±1%]
(Ω)
C1 [±10%]
(nF)
C2 [±10%]
(pF)
TYPICAL
LOCK TIME
(µs)†
x4
16.3−41.6
65−167
32.5−83
60.4
27
560
75
† _{Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the}
typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
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