TMS320C6421_07 Datasheet, PDF (66/227 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346B – JANUARY 2007 – REVISED APRIL 2007
www.ti.com
Table 3-2. VDD3P3V_PWDN Register Bit Descriptions (continued)
BIT
NAME
DESCRIPTION
UART0 Data Block I/O Power Down Control.
Controls the power of the 2 I/O pins in the UART0 Data Block.
10
UR0DAT
0 = I/O pins powered up.
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].
Timer1 Block I/O Power Down Control.
Controls the power of the 2 I/O pins in the Timer1 Block.
9
TIMER1
0 = I/O pins powered up.
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].
Timer0 Block I/O Power Down Control.
Controls the power of the 2 I/O pins in the Timer0 Block.
8
TIMER0
0 = I/O pins powered up.
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].
Serial Port Block I/O Power Down Control.
Controls the power of the 12 I/O pins in the Serial Port Block (Serial Port Sub-Block 0 and
Serial Port Sub-Block 1).
7
SP
0 = I/O pins powered up.
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].
PWM1 Block I/O Power Down Control.
Controls the power of the 1 I/O pin in the PWM1 Block.
6
PWM1
0 = I/O pins powered up.
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].
GPIO Block I/O Power Down Control.
Controls the power of the 4 I/O pins in the GPIO Block: GP[3:0].
5
GPIO
Note: GPIO Block contains standalone GPIO pins and is not a pin mux group.
0 = I/O pins powered up [default].
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z).
Host Block I/O Power Down Control.
Controls the power of the 27 I/O pins in the Host Block.
4
HOST
0 = I/O pins powered up [default].
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z).
EMIFA Sub-Block 2 I/O Power Down Control.
Controls the power of the 3 I/O pins in the EMIFA Sub-Block 2.
3
EMBK2
0 = I/O pins powered up [default].
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z).
EMIFA Sub-Block 1 I/O Power Down Control.
Controls the power of the 29 I/O pins in the EMIFA Sub-Block 1.
2
EMBK1
0 = I/O pins powered up [default].
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z).
EMIFA Sub-Block 0 I/O Power Down Control.
Controls the power of the 21 I/O pins in the EMIFA Sub-Block 0.
1
EMBK0
0 = I/O pins powered up [default].
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z).
CLKOUT Block I/O Power Down Control.
Controls the power of the 1 I/O pin in the CLKOUT Block.
0
CLKOUT
0 = I/O pins powered up [default].
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z).
66
Device Configurations
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