TMS320C6421_07 Datasheet, PDF (35/227 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346B – JANUARY 2007 – REVISED APRIL 2007
Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode 2, AEM[2:0] = 010) (continued)
SIGNAL
NAME
ZWT
NO.
EM_A[21]/GP[34] D12
EM_A[20]/GP[44] C12
EM_A[19]/GP[45] B12
EM_A[18]/GP[46] D11
EM_A[17]/GP[47] A11
EM_A[16]/GP[48] C11
EM_A[15]/GP[49] B11
EM_A[14]/GP[50] A10
EM_A[13]/GP[51] B10
EM_A[12]/GP[89] D10
EM_A[11]/GP[90] C10
EM_A[10]/GP[91] A9
EM_A[9]/GP[92] D9
EM_A[8]/GP[93] B9
EM_A[7]/GP[94] C9
EM_A[6]/GP[95] D8
EM_A[5]/GP[96] B8
ZDU
NO.
C16
C15
C14
A14
B14
B13
C13
A13
A12
B12
C12
B11
C11
A11
C10
B10
A10
TYPE ⁽¹⁾
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
OTHER ^{(2) (3)}
DESCRIPTION
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 21 output
EM_A[21].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 20 output
EM_A[20].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 19 output
EM_A[19].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 18 output
EM_A[18].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 17 output
EM_A[17].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 16 output
EM_A[16].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 15 output
EM_A[15].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 14 output
EM_A[14].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 13 output
EM_A[13].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 12 output
EM_A[12].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 11 output
EM_A[11].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 10 output
EM_A[10].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 9 output EM_A[9].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 8 output EM_A[8].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 7 output EM_A[7].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 6 output EM_A[6].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 5 output EM_A[5].
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