ADC10D1000QML-SP Datasheet, PDF (65/70 Pages) Texas Instruments – ADC10D1000QML Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter

ADC10D1000QML-SP
www.ti.com
SNAS466F – FEBRUARY 2009 – REVISED APRIL 2013
Table 6-29. AutoSync
Addr: Eh (1110b)
Default Values: 0003h
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
DRC(9:0)
Res.
SP(1:0)
ES DOC DR
DV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Bits 15:6
Bit 5
Bits 4:3
Bit 2
Bit 1
Bit 0
DRC(9:0): Delay Reference Clock (9:0). These bits may be used to increase the delay on the input reference clock when
synchronizing multiple ADCs. The minimum delay is 0s (0d) to 1000 ps (629d). The delay remains the maximum of 1000 ps for
any codes above or equal to 639d.
Reserved. Must be set to 0b.
SP(1:0): Select Phase. These bits select the phase of the reference clock which is latched. The codes correspond to the
following phase shift:
00 = 0°
01 = 90°
10 = 180°
11 = 270°
ES: Enable Slave. Set this bit to 1b to enable the Slave Mode of operation. In this mode, the internal divided clocks are
synchronized with the reference clock coming from the master ADC. The master clock is applied on the input pins RCLK+/-. If
this bit is set to 0b, then the device is in Master Mode.
DOC: Disable Output reference Clocks. Setting this bit to 0b sends a CLK/4 signal on RCOut1 and RCOut2. The default
setting of 1b disables these output drivers. This bit functions as described, regardless of whether the device is operating in
Master or Slave Mode, as determined by ES (Bit 2).
DR: Disable Reset. The default setting of 0b leaves the DCLK_RST functionality disabled. Set this bit to 1b to enable
DCLK_RST functionality.
Table 6-30. Reserved
Addr: Fh (1111b)
Default Values: XXXXh
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
DV
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bits 15:0 Reserved. Do not write.
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Application Information
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