PCI2050B Datasheet, PDF (64/87 Pages) Texas Instruments – PCI-TO-PCI BRIDGE

5.4 P_SERR Event Disable Register
The P_SERR event disable register is used to enable/disable the SERR event on the primary interface. All events
are enabled by default.
Bit
Name
Type
Default
7
6
5
4
3
2
1
0
P_SERR event disable
R
R/W
R/W
R/W
R/W
R/W
R/W
R
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
P_SERR event disable
Read-only, Read/Write
64h
00h
Table 5−4. P_SERR Event Disable Register Description
BIT TYPE
FUNCTION
7
R Reserved. Bit 7 returns 0 when read.
Master delayed read time-out.
6
R/W
0 = P_SERR signaled on a master time-out after 224 retries on a delayed read (default).
1 = P_SERR is not signaled on a master time-out.
Master delayed write time-out.
5
R/W
0 = P_SERR signaled on a master time-out after 224 retries on a delayed write (default).
1 = P_SERR is not signaled on a master time-out.
Master abort on posted write transactions. When set, bit 4 enables P_SERR reporting on master aborts on posted write
4
R/W
transactions.
0 = Master aborts on posted writes enabled (default)
1 = Master aborts on posted writes disabled
Target abort on posted writes. When set, bit 3 enables P_SERR reporting on target aborts on posted write transactions.
3
R/W
0 = Target aborts on posted writes enabled (default).
1 = Target aborts on posted writes disabled.
Master posted write time-out.
2
R/W
0 = P_SERR signaled on a master time-out after 224 retries on a posted write (default).
1 = P_SERR is not signaled on a master time-out.
Posted write parity error.
1
R/W
0 = P_SERR signaled on a posted write parity error (default).
1 = P_SERR is not signaled on a posted write parity error.
0
R Reserved. Bit 0 returns 0 when read.
5−4