PCI2050B Datasheet, PDF (32/87 Pages) Texas Instruments – PCI-TO-PCI BRIDGE

Because type 1 configuration cycles are issued to devices on subordinate buses, the bridge claims type 1 cycles
based on the bus number of the destination bus. The P_AD bus encoding during the address phase of a type 1 cycle
is shown in Figure 3−3. The device number and bus number fields define the destination bus and device for the cycle.
31
24 23
16 15
11 10 8 7
2 10
Reserved
Bus Number
Device
Number
Function
Number
Register
Number
01
Figure 3−3. PCI AD31−AD0 During Address Phase of a Type 1 Configuration Cycle
Several bridge configuration registers shown in Table 4−1 are significant when decoding and claiming type 1
configuration cycles. The destination bus number encoded on the P_AD bus is compared to the values programmed
in the bridge configuration registers 18h, 19h, and 1Ah, which are the primary bus number, secondary bus number,
and subordinate bus number registers, respectively. These registers default to 00h and are programmed by host
software to reflect the bus hierarchy in the system (see Figure 3−4 for an example of a system bus hierarchy and how
the PCI2050B bus number registers would be programmed in this case).
PCI Bus 0
PCI2050B
Primary Bus
00h
Secondary Bus
01h
Subordinate Bus 02h
PCI Bus 1
PCI2050B
Primary Bus
00h
Secondary Bus
03h
Subordinate Bus 03h
PCI Bus 3
PCI2050B
Primary Bus
01h
Secondary Bus
02h
Subordinate Bus 02h
PCI Bus 2
Figure 3−4. Bus Hierarchy and Numbering
When the PCI2050B bridge claims a type 1 configuration cycle that has a bus number equal to its secondary bus
number, the PCI2050B bridge converts the type 1 configuration cycle to a type 0 configuration cycle and asserts the
proper S_AD line as the IDSEL (see Table 3−2). All other type 1 transactions that access a bus number greater than
the bridge secondary bus number but less than or equal to its subordinate bus number are forwarded as type 1
configuration cycles.
3−4