XIO2000 Datasheet, PDF (63/150 Pages) Texas Instruments – XIO2000 PCI Express to PCI Bus Translation Bridge

Classic PCI Configuration Space
4.24 I/O Base Upper 16-Bit Register
This read/write register specifies the upper 16 bits of the I/O base register. See Table 4−15 for a complete
description of the register contents.
PCI register offset:
Register type:
Default value:
30h
Read/Write
0000h
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−15. I/O Base Upper 16-Bit Register Description
BIT FIELD NAME ACCESS
DESCRIPTION
15:0
IOBASE
I/O base upper 16 bits. Defines the upper 16 bits of the lowest address of the I/O address range
RW that determines when to forward I/O transactions downstream. These bits correspond to address
bits [31:20] in the I/O address. The lower 20 bits are assumed to be 00000h.
4.25 I/O Limit Upper 16-Bit Register
This read/write register specifies the upper 16 bits of the I/O limit register. See Table 4−16 for a complete
description of the register contents.
PCI register offset:
Register type:
Default value:
32h
Read/Write
0000h
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−16. I/O Limit Upper 16-Bit Register Description
BIT FIELD NAME ACCESS
DESCRIPTION
15:0
IOLIMIT
I/O limit upper 16 bits. Defines the upper 16 bits of the top address of the I/O address range that
RW determines when to forward I/O transactions downstream. These bits correspond to address
bits [31:20] in the I/O address. The lower 20 bits are assumed to be FFFFFh.
4.26 Capabilities Pointer Register
This read-only register provides a pointer into the PCI configuration header where the PCI power management
block resides. Since the PCI power management registers begin at 50h, this register is hardwired to 50h.
PCI register offset:
Register type:
Default value:
34h
Read-only
50h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE 0
1
0
1
0
0
0
0
November 2005
SCPS097B
51