XIO2000 Datasheet, PDF (54/150 Pages) Texas Instruments – XIO2000 PCI Express to PCI Bus Translation Bridge

Classic PCI Configuration Space
4.3 Command Register
The command register controls how the bridge behaves on the PCI Express interface. See Table 4−2 for a
complete description of the register contents.
PCI register offset:
Register type:
Default value:
04h
Read-only, Read/Write
0000h
BIT
15:11
10
9
8
7
6
5
4
3
2
1
0
BIT NUMBER
RESET STATE
FIELD NAME
RSVD
INT_DISABLE
FBB_ENB
SERR_ENB
STEP_ENB
PERR_ENB
VGA_ENB
MWI_ENB
SPECIAL
MASTER_ENB
MEMORY_ENB
IO_ENB
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−2. Command Register Description
ACCESS
DESCRIPTION
R
Reserved. Returns 00000b when read.
R
INTx disable. This bit enables device specific interrupts. Since the bridge does not generate any
internal interrupts, this bit is read-only 0b.
Fast back-to-back enable. The bridge does not generate fast back-to-back transactions;
R
therefore, this bit returns 0b when read.
SERR enable bit. When this bit is set, the bridge can signal fatal and nonfatal errors on the PCI
Express interface on behalf of SERR assertions detected on the PCI bus.
RW
0 = Disable the reporting of nonfatal errors and fatal errors (default)
1 = Enable the reporting of nonfatal errors and fatal errors
R
Address/data stepping control. The bridge does not support address/data stepping, and this bit is
hardwired to 0b.
Controls the setting of bit 8 (DATAPAR) in the status register (offset 06h, see Section 4.4) in
response to a received poisoned TLP from PCI Express. A received poisoned TLP is forwarded
RW ^{with bad parity to conventional PCI regardless of the setting of this bit.}
0 = Disables the setting of the master data parity error bit (default)
1 = Enables the setting of the master data parity error bit
R
VGA palette snoop enable. The bridge does not support VGA palette snooping; therefore, this bit
returns 0b when read.
Memory write and invalidate enable. When this bit is set, the bridge translates PCI Express
memory write requests into memory write and invalidate transactions on the PCI interface.
RW
0 = Disable the promotion to memory write and invalidate (default)
1 = Enable the promotion to memory write and invalidate
R
Special cycle enable. The bridge does not respond to special cycle transactions; therefore, this
bit returns 0b when read.
Bus master enable. When this bit is set, the bridge is enabled to initiate transactions on the PCI
Express interface.
RW
0 = PCI Express interface cannot initiate transactions. The bridge must disable the response
to memory and I/O transactions on the PCI interface (default).
1 = PCI Express interface can initiate transactions. The bridge can forward memory and I/O
transactions from PCI secondary interface to the PCI Express interface.
Memory space enable. Setting this bit enables the bridge to respond to memory transactions on
the PCI Express interface.
RW
0 = PCI Express receiver cannot process downstream memory transactions and must
respond with an unsupported request (default)
1 = PCI Express receiver can process downstream memory transactions. The bridge can
forward memory transactions to the PCI interface.
I/O space enable. Setting this bit enables the bridge to respond to I/O transactions on the PCI
Express interface.
RW
0 = PCI Express receiver cannot process downstream I/O transactions and must respond
with an unsupported request (default)
1 = PCI Express receiver can process downstream I/O transactions. The bridge can forward
I/O transactions to the PCI interface.
42 SCPS097B
November 2005