UCD3138A_15 Datasheet, PDF (63/83 Pages) Texas Instruments – Highly Integrated Digital Controller for Isolated Power

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UCD3138A
SLUSC66B – MARCH 2015 – REVISED MAY 2015
In addition, it is necessary to set the D2S_COMP_EN bit in the EADCCTRL register. This is for enabling
the differential to single ended comparator function. The front end diagram leaves it out for simplicity, but
the connection between the DAC and the EADC amplifier is actually differential. The PCMC comparator,
however, is single ended. So a conversion is necessary as shown in Figure 7-9.
AFE_GAIN
EA P0
E AN0
2^AFE_GAIN
DAC0
10 bit DAC
1. 5625mV/ LSB
Differential to
Single Ended
2^3-AFE_GAIN
6 bit ADC
8mV/LSB
EADC
X
Averaging
Signed 9 bit result
(error) 1 mV /LSB
SAR/ Prebias
Ramp
Filter x
CPCC
Σ
Value
Dither
4 bit dithering gives 14 bits of effective resolution
97.65625μV/LSB effective resolution
Absolute Value
Calculation
10 bit result
1.5625mV/LSB
Peak Current
Detected
Peak Current Mode
Comparator
Figure 7-9. Differential to Single-Ended Comparator Function
The EADC_MODE bit in EADCCTRL should be set to a 5 for peak current mode.
The peak current detection signal next goes to the Loop Mux. The Fault Mux has only 1 APCM input, but
there are 3 front ends. So the PCM_FE_SEL bits in APCMCTRL must be used to select which front end is
used:
LoopMuxRegs.APCMCTRL.bit.PCM_FE_SEL = 2; // use FE2 for PCM */
The PCM_EN bit must also be set.
LoopMuxRegs.APCMCTRL.bit.PCM_EN = 1; // Enable PCM
Next the Fault Mux is used to enable the APCM bit to the CLIM/CBC signal to the DPWM. There are 4
DPWMxCLIM registers, one for each DPWM. The ANALOG_PCM_EN bit must be set in each one to
connect the PCM detection signal to the CLIM/CBC signal on each DPWM. For the latest configuration
information on all of these bits, consult the appropriate EVM firmware. To avoid errors, it is best to
configure your hardware design using the same DPWMs, filters, and front ends for the same functions as
the EVM.
DPWM timing is used to trigger the start of the ramp. This is selected by the FECTRLxMUX registers in
the Loop Mux. DPWMx_FRAME_SYNC_EN bits, when set, cause the ramp to be triggered at the start of
the DPWM period.
7.2.6.3 Peak Current Mode (PCM)
There is one peak current mode control module in the device however any front end can be configured to
use this module.
Copyright © 2015, Texas Instruments Incorporated
Application, Implementation, and Layout
63
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