UCD3138A_15 Datasheet, PDF (36/83 Pages) Texas Instruments – Highly Integrated Digital Controller for Isolated Power

UCD3138A
SLUSC66B – MARCH 2015 – REVISED MAY 2015
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6.6 Sync FET Ramp and IDE Calculation
The UCD3138A has built in logic for controlling MOSFETs for synchronous rectification (Sync FETs). This
comes in two forms:
• Sync FET ramp
• Ideal Diode Emulation (IDE) calculation
When starting up a power supply, sometimes there is already a voltage on the output – this is called
prebias. It is difficult to calculate the ideal Sync FET on-time for this case. If it is not calculated correctly, it
may pull down the prebias voltage, causing the power supply to sink current.
To avoid this, Sync FETs are not turned on until the power supply has ramped up to the nominal voltage.
The Sync FETs are turned on gradually in order to avoid an output voltage glitch. The Sync FET Ramp
logic can be used to turn them on at a rate below the bandwidth of the filter.
In discontinuous mode, the ideal on-time for the Sync FETs is a function of V_IN, V_OUT, and the primary side
duty cycle (D). The IDE logic in the UCD3138A takes V_IN and V_OUT data from the firmware and combines it
with D data from the filter hardware. It uses this information to calculate the ideal on-time for the Sync
FETs.
6.7 Automatic Mode Switching
Automatic Mode switching enables the DPWM module to switch between modes automatically. This is
useful to increase efficiency and power range. The following paragraphs describe phase-shifted full bridge
and LLC examples:
6.7.1 Phase Shifted Full Bridge Example
Phase shifted full bridge topologies are shown in Figure 6-6 and Figure 6-7.
DPWM3A
(QB1)
DPWM3B
(QT1)
DPWM2A
(QT2)
DPWM2B
(QB2)
VTrans
DPWM1B
(QSYN1,3)
DPWM0B
(QSYN2,4)
IPRI
36
Detailed Description
Figure 6-6. Phase Shifted Full Bridge
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