TMS320LC2401A Datasheet, PDF (62/88 Pages) Texas Instruments – DSP CONTROLLERS

TMS320LF2401A, TMS320LC2401A
DSP CONTROLLERS
SPRS161H − MARCH 2001 − REVISED MARCH 2004
external reference crystal/clock with PLL circuit enabled
timing with the PLL circuit enabled
PARAMETER
MIN MAX
Resonator
4
13
fx
Input clock frequency†
Crystal
4
20
CLKIN
4
20
† _{Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.}
UNIT
MHz
switching characteristics over recommended operating conditions [H = 0.5 t_c(CO)] (see Figure 25)
tc(CO)
PARAMETER
Cycle time, CLKOUT
PLL MODE
X4 mode†
MIN TYP
25
MAX
UNIT
ns
tf(CO)
Fall time, CLKOUT
4
ns
tr(CO)
tw(COL)
tw(COH)
Rise time, CLKOUT
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
4
ns
LF2401A X4 mode† @ 2 mA load H −3
H
H +3 ns
LF2401A X4 mode† @ 2 mA load H −3
H
H +3 ns
tw(COL)
Pulse duration, CLKOUT low
LC2401A X4 mode† @ 2 mA load H −5
H
H +5 ns
tw(COH)
Pulse duration, CLKOUT high
LC2401A X4 mode† @ 2 mA load H −5
H
H +5 ns
† _{Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 2 MHz minimum.}
timing requirements (see Figure 25)
tc(Cl)
tf(Cl)
tr(Cl)
tw(CIL)
tw(CIH)
Cycle time, XTAL1/CLKIN
Fall time, XTAL1/CLKIN
Rise time, XTAL1/CLKIN
Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl)
Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl)
MIN MAX
250
5
5
40
60
40
60
UNIT
ns
ns
ns
%
%
XTAL1/CLKIN
CLKOUT
tw(CIH)
tw(COH)
tc(CO)
tc(CI)
tf(Cl)
tw(CIL)
tr(Cl)
tw(COL) _tr(CO)
tf(CO)
Figure 25. CLKIN-to-CLKOUT Timing With PLL and External Clock in ×4 Mode
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