F28M36P63B2 Datasheet, PDF (62/202 Pages) Texas Instruments – Concerto Microcontrollers

F28M36P63B2, F28M36P63C2
F28M36P53B2, F28M36P53C2, F28M36P33B2, F28M36P33C2
SPRS825 – OCTOBER 2012
www.ti.com
2.16 GPIOs and Other Pins
Most Concerto external pins are shared among many internal peripherals. This sharing of pins is
accomplished through several I/O muxes where a specific physical pin can be assigned to selected
signals of internal peripherals.
Most of the I/O pins of the Concerto™ MCU can also be configured as programmable GPIOs. Exceptions
include the X1 and X2 oscillator inputs; the XRS digital reset and ARS analog reset; the VREG12EN and
VREG18EN internal voltage regulator enables; and five JTAG pins. The 144 primary GPIOs are grouped
in 2 programmable blocks: GPIO_MUX1 block (136 pins) and GPIO_MUX2 block (8 pins). Additionally,
eight secondary GPIOs are available through the AIO_MUX1 block (four pins) and AIO_MUX2 block (four
pins). Figure 2-13 shows the GPIOs and other pins.
2.16.1 GPIO_MUX1
One-hundred and thirty-six pins of the GPIO_MUX1 block can be selectively mapped through
corresponding sets of registers to all Cortex™-M3 peripherals, to all C28x peripherals, to 136 General-
Purpose Inputs, to 136 General-Purpose Outputs, or a mixture of all of the above. The first 64 pins of
GPIO_MUX1 (GPIO0–GPIO63) can also be mapped to 12 ePWM Trip Inputs, 6 eCAP inputs, 3 External
Interrupts to the C28x PIE, and the C28x Standby Mode Wakeup signal (LMPWAKE). Additionally, each
GPIO_MUX1 pin can have a pullup enabled or disabled. By default, all pullups and outputs are disabled
on reset, and all pins of the GPIO_MUX1 block are mapped to Cortex™-M3 peripherals (and not to C28x
peripherals).
Figure 2-14 shows the internal structure of GPIO_MUX1. The blue blocks represent the Master
Subsystem side of GPIO_MUX1, and the green blocks are the Control Subsystem side. The grey block in
the center, Pin-Level Mux, is where the GPIO_MUX1 pins are individually assigned between the two
subsystems, based on how the configuration registers are programmed in the blue and green blocks (see
Figure 2-15 for the configuration registers).
Pin-Level Mux assigns Master Subsystem peripheral signals, Control Subsystem peripheral signals, or
GPIOs to the 136 GPIO_MUX1 pins. In addition to connecting peripheral I/Os of the two subsystems to
pins, the Pin-Level Mux also provides other signals to the subsystems: XCLKIN and GPIO[S:A] IRQ
signals to the Master Subsystem, plus GPTRIP[12:1] and GPI[63:0] signals to the Control Subsystem.
XCLKIN carries a clock from an external pin to USB PLL and CAN modules. The 17 GPIO[S:A] IRQ
signals are interrupt requests from selected external pins to the NVIC interrupt controller. The 12
GPTRIP[12:1] signals carry trip events from selected external pins to C28x control peripherals—ePWM,
eCAP, and eQEP. Sixty-four GPI signals go to the C28x LPM GPIO Select block where one of them can
be selected to wake up the C28x CPU from Low-Power Mode. One-hundred and thirty-six (136) GPI
signals go to the C28x QUAL block where they can be configured with a qualification sampling period (see
Figure 2-15).
The configuration registers for the muxing of Master Subsystem peripherals are organized in 17 sets
(A–S), with each set being responsible for eight pins. The first nine sets of these registers (A–J) are
programmable by the Cortex™-M3 CPU via the AHB bus or the APB bus. The remaining sets of registers
(K–S) are programmable by the AHB bus only. The configuration register for the muxing of Control
Subsystem peripherals are organized in five sets (A–E), with each set being responsible for up to 32 pins.
These registers are programmable by the C28x CPU via the C28x CPU bus. Figure 2-15 shows set A of
the Master Subsystem GPIO configuration registers, set A of the Control Subsystem registers, and the
muxing logic for one GPIO pin as driven by these registers.
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