ADS6445-EP Datasheet, PDF (61/71 Pages) Texas Instruments – QUAD CHANNEL, 14 BIT, 125 MSPS ADC WITH SERIAL LVDS OUTPUTS

ADS6445-EP
www.ti.com ............................................................................................................................................................................................ SLAS573 – FEBRUARY 2008
SERIALIZATION
14×
SAMPLING
FREQUENCY
MSPS
65
40
20
10
65
40
16×
20
10
Table 30. Timing for 2-Wire Interface, SDR Bit Clock
DATA SETUP TIME, t_su
ns
DATA HOLD TIME, t_h
ns
MIN
TYP
MAX
MIN
TYP
MAX
MIN
0.8
1
1
1.2
1.5
1.7
1.6
1.8
3.4
3.4
3.6
3.3
3.5
6.9
7.2
6.6
6.9
3.7
0.65
0.85
0.8
1.0
1.3
1.5
1.4
1.6
3.4
2.8
3.0
2.8
3.0
6.0
6.3
5.8
6.1
3.7
t_delay
ns
TYP
F_s ≥ 40 MSPS
4.4
F_s < 40 MSPS
5.2
F_s ≥ 40 MSPS
4.4
F_s < 40 MSPS
5.2
MAX
5.4
6.7
5.4
6.7
SAMPLING FREQUENCY
MSPS
≥ 65
Table 31. Output Jitter (applies to all interface options)
BIT CLOCK JITTER, CYCLE-CYCLE
ps, peak-peak
MIN
TYP
MAX
350
FRAME CLOCK JITTER, CYCLE-CYCLE
ps, peak-peak
MIN
TYP
MAX
75
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