ADS6445-EP Datasheet, PDF(19/71 Page) Texas Instruments – QUAD CHANNEL, 14 BIT, 125 MSPS ADC WITH SERIAL LVDS OUTPUTS

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ADS6445-EP Datasheet, PDF (19/71 Pages) Texas Instruments – QUAD CHANNEL, 14 BIT, 125 MSPS ADC WITH SERIAL LVDS OUTPUTS

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ADS6445-EP

www.ti.com ............................................................................................................................................................................................ SLAS573 â FEBRUARY 2008

Table 16. Serial Register D

ADDRESS

BITS

A4 - A0

D10

CUSTOM PATTERN (LOWER 11 BITS)

D10 - D0

<CUSTOM A> Lower 11 bits of custom pattern <D10>â¦<D0>

Table 17. Serial Register E

ADDRESS

BITS

A4 - A0

D10

FINE GAIN CONTROL (1 dB to 6 dB)

CUSTOM PATTERN (UPPER 3 BITS)

D4 - D0

<CUSTOM B> Upper 3 bits of custom pattern <D13>â¦<D11>

D10-D8

000

001

010

011

100

101

110

<FINE GAIN> Fine gain control

0 dB Gain (full-scale range = 2.00 VPP)

1 dB Gain (full-scale range = 1.78 VPP)

2 dB Gain (full-scale range = 1.59 VPP)

3 dB Gain (full-scale range = 1.42 VPP)

4 dB Gain (full-scale range = 1.26 VPP)

5 dB Gain (full-scale range = 1.12 VPP)

6 dB Gain (full-scale range = 1.00 VPP)

ADDRESS

A4 - A0

D10

<OVRD>

OVER-RIDE

BITE

Table 18. Serial Register F

BITS

<COARSE FALLING OR

BYTE-WISE

BIT-WISE

MSB OR

LSB FIRST

GAIN>

COURSE

GAIN

RISING BIT

CLOCK

CAPTURE

ENABLE

EDGE

14 BIT OR

16 BIT

SERIALIZE

DDR OR

SDR BIT

CLOCK

1-WIRE OR

2- WIRE

INTERFACE

Interface selection

1-Wire interface

2-Wire interface

Bit clock selection (only in 2-wire interface)

DDR Bit clock

SDR Bit clock

Serialization factor selection

14X Serialization

16X Serialization

Bit clock capture edge (only when SDR bit clock is selected, D1 = 1)

Capture data with falling edge of bit clock

Capture data with rising edge of bit clock

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