TMS320BC51 Datasheet, PDF (60/87 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
MEMORY AND PARALLEL I/O INTERFACE WRITE
switching characteristics over recommended operating conditions [H = 0.5t_c(CO)] (’320C5x only)
(see Figure 15)
PARAMETER
tsu(AV-WEL)
tsu(WDV-WEH)
th(WEH-AV)
th(WEH-WDV)
tw(WEL)
tw(WEH)
td(CO-ST)
td(CO-WE)
td(WEH-RDL)
ten(WEL-BUd)
Setup time, address valid
before WE low†
Setup time, write data
valid before WE high
Hold time, address valid
after WE high†
Hold time, write data valid
after WE high
Pulse duration, WE low§¶
Pulse duration, WE high§
Delay time, CLKOUT1 to
STRB rising or falling
edge§
Delay time, CLKOUT1 to
WE rising or falling edge§
Delay time, WE high to
RD low
Enable time, WE low to
data bus driven
’320C5x-40
MIN MAX
H – 5‡
2H – 20 2H§¶
H – 10‡
H – 5 H + 10§
2H – 2 2H + 2§
2H – 2
–1
3
0
4
3H – 10
– 5§
’320C5x-57
MIN MAX
H – 5‡
2H – 20 2H§¶
H – 10‡
H – 5 H + 10§
2H – 2 2H + 2§
2H – 2
–2
2
–1
3
3H – 10
– 5§
’320C5x-80
MIN MAX
H – 4‡
’320C5x-100
MIN MAX
H – 3‡
2H – 14 2H§¶ 2H – 14 2H§¶
H – 7‡
H – 7‡
H – 4 H + 7§
2H – 2 2H + 2
2H – 2
H – 4 H + 7§
2H – 2 2H + 2
2H – 2
–2
2
–2
2
–1
3
–1
3
3H – 7
– 4§
3H – 7
– 4§
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
switching characteristics over recommended operating conditions [H = 0.5t_c(CO)] (’320LC5x only)
(see Figure 15)
PARAMETER
’320LC5x-40
’320LC5x-50
’320LC5x-80
UNIT
MIN
MAX
MIN
MAX
tsu(AV-WEL)
tsu(WDV-WEH)
th(WEH-AV)
th(WEH-WDV)
tw(WEL)
tw(WEH)
Setup time, address valid before WE low†
Setup time, write data valid before WE high#
Hold time, address valid after WE high†
Hold time, write data valid after WE high
Pulse duration, WE low¶§
Pulse duration, WE high¶
H – 7‡
2H – 20
H – 10‡
H–5
2H – 4
2H – 2
2H§¶
H + 10§
2H + 2
H – 4‡
2H – 14
H – 7‡
H–4
2H – 4
2H – 2
ns
2H§¶ ns
ns
H + 7§ ns
2H + 2 ns
ns
td(WEH-RDL) Delay time, WE high to RD low
3H – 10
3H – 7
ns
td(CO-ST)
Delay time, CLKOUT1 to STRB rising or falling edge¶
0
4
–2
2 ns
td(CO-WE)
Delay time, CLKOUT1 to WE rising or falling edge¶
0
4
–1
3 ns
ten(WE-BUd) Enable time, WE to data bus driven
– 5§
– 4§
ns
† _{A0 – A15, PS, DS, IS, R / W, and BR timings are all included in timings referenced as address.}
‡ _{See Figure 16 for address bus timing variation with load capacitance.}
§ _{Values derived from characterization data and not tested}
¶ _{This value holds true for zero wait states or one software wait state only.}
# _{STRB and WE edges are 0 – 4 ns from CLKOUT1 edges on writes. Rising and falling edges of these signals track each other; tolerance of resulting}
pulsewidths is ± 2 ns, not ± 4 ns.
60
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